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author | iximeow <me@iximeow.net> | 2024-03-17 02:34:27 +0000 |
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committer | iximeow <me@iximeow.net> | 2024-03-17 02:34:27 +0000 |
commit | 79d220ce177833f7dd80e15e1094bbfbf4c6f8b1 (patch) | |
tree | 5624ca330ce94299791bab1e44421bbe596a38c1 /tests/armv8/a64.rs | |
parent | 2b0930355d87d7f195a7ff05d18b09b61a5ea490 (diff) |
system instruction and register improvements
* cN instead of crN for control registers
* # for immediates in sys/sysl instructions
* write out ARM system register names in the way the ARM reference manual says
Diffstat (limited to 'tests/armv8/a64.rs')
-rw-r--r-- | tests/armv8/a64.rs | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tests/armv8/a64.rs b/tests/armv8/a64.rs index 1d04a76..a3ec96e 100644 --- a/tests/armv8/a64.rs +++ b/tests/armv8/a64.rs @@ -4753,6 +4753,26 @@ fn test_vec_shift() { } #[test] +fn test_system() { + const TESTS: &[([u8; 4], &'static str)] = &[ + ([0x00, 0x00, 0x08, 0xd5], "sys #0x0, c0, c0, #0x0, x0"), + ([0x00, 0x00, 0x28, 0xd5], "sysl x0, #0x0, c0, c0, #0x0"), + ([0x10, 0x00, 0x08, 0xd5], "sys #0x0, c0, c0, #0x0, x16"), + ([0x10, 0x00, 0x28, 0xd5], "sysl x16, #0x0, c0, c0, #0x0"), + ([0xab, 0x03, 0x08, 0xd5], "sys #0x0, c0, c3, #0x5, x11"), + ([0xab, 0x03, 0x28, 0xd5], "sysl x11, #0x0, c0, c3, #0x5"), + ([0x00, 0x00, 0x30, 0xd5], "mrs x0, s2_0_c0_c0_0"), + ]; + let errs = run_tests(TESTS); + + for err in errs.iter() { + println!("{}", err); + } + + assert!(errs.is_empty()); +} + +#[test] fn test_pac() { const TESTS: &[([u8; 4], &'static str)] = &[ ([0x00, 0x04, 0xc1, 0xda], "pacib x0, x0"), |