diff options
| author | rva3 <rva333@protonmail.com> | 2026-02-20 03:25:33 +0200 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-02-22 03:05:53 +0000 |
| commit | 256c8128d82a5c5d99c1a114f3fb488b28d6b925 (patch) | |
| tree | b98662b05e920a59bcf419b43bec59b596726b6a /tests | |
| parent | 5f91a83b861a0c67dde9a887db7e08dafd0a5b65 (diff) | |
properly display coprocessor higher than 9
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/armv7/mod.rs | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/tests/armv7/mod.rs b/tests/armv7/mod.rs index 59dea7c..b878dd1 100644 --- a/tests/armv7/mod.rs +++ b/tests/armv7/mod.rs @@ -554,26 +554,37 @@ fn test_unconditional() { test_armv6([0x0f, 0x05, 0xed, 0xf8], "srsia sp!, 0xf"); test_armv5([0x01, 0x02, 0x03, 0xfb], "blx $+0xc0806"); test_armv5([0x01, 0x02, 0x03, 0xfa], "blx $+0xc0804"); +} + +#[test] +fn test_coproc() { test_armv5([0x12, 0x34, 0xcf, 0xfc], "stc2l p4, c3, [pc], {0x12}"); + test_armv5([0x12, 0x3d, 0xcf, 0xfc], "stc2l p13, c3, [pc], {0x12}"); test_armv5([0x12, 0x34, 0xdf, 0xfc], "ldc2l p4, c3, [pc], {0x12}"); test_armv5([0x34, 0x78, 0xff, 0xfc], "ldc2l p8, c7, [pc], 0xd0"); + test_armv5([0x34, 0x7d, 0xff, 0xfc], "ldc2l p13, c7, [pc], 0xd0"); test_invalid([0x34, 0x78, 0x1f, 0xfc]); test_armv5([0x34, 0x78, 0x9f, 0xfc], "ldc2 p8, c7, [pc], {0x34}"); + test_armv5([0x34, 0x7d, 0x9f, 0xfc], "ldc2 p13, c7, [pc], {0x34}"); test_armv5([0x34, 0x78, 0xbf, 0xfc], "ldc2 p8, c7, [pc], 0xd0"); test_armv5([0x34, 0x78, 0xbf, 0xfd], "ldc2 p8, c7, [pc, 0xd0]!"); test_armv5([0x34, 0x78, 0x9f, 0xfd], "ldc2 p8, c7, [pc, 0xd0]"); - test_armv5([0x34, 0x78, 0x1f, 0xfd], "ldc2 p8, c7, [pc, -0xd0]"); - test_armv5([0x34, 0x78, 0xdf, 0xfc], "ldc2l p8, c7, [pc], {0x34}"); test_armv6([0x34, 0x78, 0x5a, 0xfc], "mrrc2 p8, 3, r7, r10, c4"); + test_armv6([0x34, 0x7d, 0x5a, 0xfc], "mrrc2 p13, 3, r7, r10, c4"); // Rt/Rt2 may not be r15 test_invalid([0x34, 0x78, 0x5f, 0xfc]); test_armv6([0x34, 0x78, 0x4a, 0xfc], "mcrr2 p8, 3, r7, r10, c4"); + test_armv6([0x34, 0x7d, 0x4a, 0xfc], "mcrr2 p13, 3, r7, r10, c4"); // Rt/Rt2 may not be r15 test_invalid([0x34, 0x78, 0x4f, 0xfc]); test_armv5([0x34, 0x78, 0x4f, 0xfe], "mcr2 p8, 2, r7, c15, c4, 1"); + test_armv5([0x34, 0x7d, 0x4f, 0xfe], "mcr2 p13, 2, r7, c15, c4, 1"); test_armv5([0x34, 0x78, 0x5f, 0xfe], "mrc2 p8, 2, r7, c15, c4, 1"); + test_armv5([0x34, 0x7d, 0x5f, 0xfe], "mrc2 p13, 2, r7, c15, c4, 1"); test_armv5([0x24, 0x78, 0x5f, 0xfe], "cdp2 p8, 5, c7, c15, c4, 1"); + test_armv5([0x24, 0x7d, 0x5f, 0xfe], "cdp2 p13, 5, c7, c15, c4, 1"); test_armv5([0x24, 0x78, 0x4f, 0xfe], "cdp2 p8, 4, c7, c15, c4, 1"); + test_armv5([0x24, 0x7d, 0x4f, 0xfe], "cdp2 p13, 4, c7, c15, c4, 1"); } #[test] |