diff options
| -rw-r--r-- | src/armv8/a64.rs | 12 | ||||
| -rw-r--r-- | test/armv8/a64.rs | 29 |
2 files changed, 35 insertions, 6 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index 8b22e3a..4dc5483 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -2402,9 +2402,9 @@ impl Display for Operand { Operand::RegPostIndex(reg, offset) => { if *offset != 0 { if *offset < 0 { - write!(fmt, "[{}], -{:#x}", Operand::RegisterOrSP(SizeCode::X, *reg), -*offset) + write!(fmt, "[{}], #-{}", Operand::RegisterOrSP(SizeCode::X, *reg), -*offset) } else { - write!(fmt, "[{}], {:#x}", Operand::RegisterOrSP(SizeCode::X, *reg), offset) + write!(fmt, "[{}], #{}", Operand::RegisterOrSP(SizeCode::X, *reg), offset) } } else { write!(fmt, "[{}]", Operand::RegisterOrSP(SizeCode::X, *reg)) @@ -8444,7 +8444,7 @@ impl Decoder<ARMv8> for InstDecoder { Opcode::LD3R, Opcode::LD4R, ]; - let opc_idx = (opcode_bits & 0x01) * 2 + S; + let opc_idx = (opcode_bits & 0x01) * 2 + R; inst.opcode = OPCODES[opc_idx as usize]; const SIZES: [SIMDSizeCode; 4] = [ SIMDSizeCode::B, @@ -8453,7 +8453,7 @@ impl Decoder<ARMv8> for InstDecoder { SIMDSizeCode::D, ]; inst.operands = [ - Operand::SIMDRegisterGroup(datasize, Rt as u16, SIZES[size as usize], opc_idx as u8), + Operand::SIMDRegisterGroup(datasize, Rt as u16, SIZES[size as usize], opc_idx as u8 + 1), Operand::RegPostIndex(Rn as u16, 0), Operand::Nothing, Operand::Nothing, @@ -8571,7 +8571,7 @@ impl Decoder<ARMv8> for InstDecoder { Opcode::LD3R, Opcode::LD4R, ]; - let opc_idx = (opcode_bits & 0x01) * 2 + S; + let opc_idx = (opcode_bits & 0x01) * 2 + R; inst.opcode = OPCODES[opc_idx as usize]; const SIZES: [SIMDSizeCode; 4] = [ SIMDSizeCode::B, @@ -8580,7 +8580,7 @@ impl Decoder<ARMv8> for InstDecoder { SIMDSizeCode::D, ]; inst.operands = [ - Operand::SIMDRegisterGroup(datasize, Rt as u16, SIZES[size as usize], opc_idx as u8), + Operand::SIMDRegisterGroup(datasize, Rt as u16, SIZES[size as usize], opc_idx as u8 + 1), if Rm == 31 { Operand::RegPostIndex(Rn as u16, ((opc_idx + 1) * (1 << size)) as i32) } else { diff --git a/test/armv8/a64.rs b/test/armv8/a64.rs index 92115e0..2523a92 100644 --- a/test/armv8/a64.rs +++ b/test/armv8/a64.rs @@ -4401,3 +4401,32 @@ fn test_stll() { assert!(errs.is_empty()); } + +#[test] +fn test_ldst_structure() { + const TESTS: &[([u8; 4], &'static str)] = &[ + ([0x00, 0xe0, 0x40, 0x0d], "ld3r {v0.8b, v1.8b, v2.8b}, [x0]"), + ]; + let errs = run_tests(TESTS); + + for err in errs.iter() { + println!("{}", err); + } + + assert!(errs.is_empty()); +} + +#[test] +fn test_tbl() { + const TESTS: &[([u8; 4], &'static str)] = &[ + ([0x00, 0x00, 0x00, 0x0e], "tbl v0.8b, {v0.16b}, v0.8b"), + ([0x20, 0x00, 0x00, 0x0e], "tbl v0.8b, {v1.16b}, v0.8b"), + ]; + let errs = run_tests(TESTS); + + for err in errs.iter() { + println!("{}", err); + } + + assert!(errs.is_empty()); +} |