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-rw-r--r--src/armv8/a64.rs20
-rw-r--r--tests/armv8/a64.rs16
2 files changed, 23 insertions, 13 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index c697c76..4cd91da 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -444,21 +444,15 @@ impl Display for Instruction {
},
Opcode::UBFM => {
// TODO: handle ubfx alias
- if let Operand::Immediate(0) = self.operands[2] {
- let newdest = if let Operand::Register(_size, destnum) = self.operands[0] {
- Operand::Register(SizeCode::W, destnum)
- } else {
- unreachable!("operand 1 is always a register");
- };
- let newsrc = if let Operand::Register(_size, srcnum) = self.operands[1] {
- Operand::Register(SizeCode::W, srcnum)
- } else {
- unreachable!("operand 1 is always a register");
- };
+ if let (
+ Operand::Register(SizeCode::W, destnum),
+ Operand::Register(SizeCode::W, srcnum),
+ Operand::Immediate(0)
+ ) = (self.operands[0], self.operands[1], self.operands[2]) {
if let Operand::Immediate(7) = self.operands[3] {
- return write!(fmt, "uxtb {}, {}", newdest, newsrc);
+ return write!(fmt, "uxtb {}, {}", self.operands[0], self.operands[1]);
} else if let Operand::Immediate(15) = self.operands[3] {
- return write!(fmt, "uxth {}, {}", newdest, newsrc);
+ return write!(fmt, "uxth {}, {}", self.operands[0], self.operands[1]);
}
}
if let Operand::Immediate(imms) = self.operands[3] {
diff --git a/tests/armv8/a64.rs b/tests/armv8/a64.rs
index 74bb89f..0e76ef6 100644
--- a/tests/armv8/a64.rs
+++ b/tests/armv8/a64.rs
@@ -4931,3 +4931,19 @@ fn test_misc() {
assert!(errs.is_empty());
}
+
+#[test]
+fn test_bitfield() {
+ const TESTS: &[([u8; 4], &'static str)] = &[
+ ([0x00, 0x1c, 0x40, 0xd3], "ubfx x0, x0, #0x0, #0x8"),
+ ([0x1f, 0x1c, 0x00, 0x53], "uxtb wzr, w0"),
+ ];
+
+ let errs = run_tests(TESTS);
+
+ for err in errs.iter() {
+ println!("{}", err);
+ }
+
+ assert!(errs.is_empty());
+}