diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/armv7.rs | 10 | ||||
| -rw-r--r-- | src/armv7/thumb.rs | 21 |
2 files changed, 29 insertions, 2 deletions
diff --git a/src/armv7.rs b/src/armv7.rs index a67067f..01c1827 100644 --- a/src/armv7.rs +++ b/src/armv7.rs @@ -161,6 +161,16 @@ pub enum Opcode { SEV, CSDB, YIELD, + /// ARM generally does not have a blanket `hint #123` instruction, but does have a section of + /// opcode space reserved for architectural hinting. this is where `nop`, `yield`, `wfe`, etc + /// are defined. those "hints" have defined architectural (non-)effects and have their own + /// Opcode variants. for the bit patterns not yet defined to a specific hint, the ARM reference + /// manual says the execution on historical processors is as if `op2 is set to 0b00000000` + /// (that is, `nop`), but that software must not use these unallocated encodings. + /// + /// so, `hint` exists to describe these "execute-as-nop" instructions which have at least one + /// operand describing possible future behavior. instructions that are defined in this space + /// are expected to be decoded as distinct opcodes. HINT, NOP, LEAVEX, diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs index ab3f94b..cba18a4 100644 --- a/src/armv7/thumb.rs +++ b/src/armv7/thumb.rs @@ -1808,8 +1808,25 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d Operand::Nothing, ]; } - _ => { - return Err(DecodeError::Undefined); + hint => { + // from DDI0406 C.d (v7): + // > Encodings with op1 set to 0b000 and a value of + // > op2 that is not shown in the table are + // > unallocated hints, and behave as if op2 is set + // > to 0b00000000. These unallocated hint encodings + // > are reserved and software must not use them. + // + // so.. it would be "right" to report these as + // "nop", but the hint operand is interesting for + // forward compatibility. guess that means we + // invent a "hint" instruction too? + inst.opcode = Opcode::HINT; + inst.operands = [ + Operand::Imm12(hint as u16), + Operand::Nothing, + Operand::Nothing, + Operand::Nothing, + ]; } } } |