diff options
Diffstat (limited to 'test/armv8/a64.rs')
| -rw-r--r-- | test/armv8/a64.rs | 88 |
1 files changed, 44 insertions, 44 deletions
diff --git a/test/armv8/a64.rs b/test/armv8/a64.rs index 8de1f99..4d2815a 100644 --- a/test/armv8/a64.rs +++ b/test/armv8/a64.rs @@ -110,7 +110,7 @@ fn test_decode_str_ldr() { operands: [ Operand::Register(SizeCode::X, 29), Operand::Register(SizeCode::X, 30), - Operand::RegPreIndex(31, -0x20), + Operand::RegPreIndex(31, -0x20, true), Operand::Nothing, ] } @@ -2839,11 +2839,11 @@ fn test_openblas_simd_loadstore() { ([0x20, 0x04, 0xc1, 0x3c], "ldr q0, [x1], 0x10"), ([0x04, 0x06, 0xc1, 0x3c], "ldr q4, [x16], 0x10"), ([0x05, 0x06, 0xc1, 0x3c], "ldr q5, [x16], 0x10"), - ([0x34, 0x00, 0xc2, 0x3c], "ldur q20, [x1, 32]"), - ([0x3c, 0x00, 0xc6, 0x3c], "ldur q28, [x1, 96]"), - ([0x06, 0x02, 0xc6, 0x3c], "ldur q6, [x16, 96]"), - ([0x3e, 0x00, 0xc7, 0x3c], "ldur q30, [x1, 112]"), - ([0x07, 0x02, 0xc7, 0x3c], "ldur q7, [x16, 112]"), + ([0x34, 0x00, 0xc2, 0x3c], "ldur q20, [x1, 0x20]"), + ([0x3c, 0x00, 0xc6, 0x3c], "ldur q28, [x1, 0x60]"), + ([0x06, 0x02, 0xc6, 0x3c], "ldur q6, [x16, 0x60]"), + ([0x3e, 0x00, 0xc7, 0x3c], "ldur q30, [x1, 0x70]"), + ([0x07, 0x02, 0xc7, 0x3c], "ldur q7, [x16, 0x70]"), ([0x44, 0x00, 0xdf, 0x3c], "ldur q4, [x2, -0x10]"), ([0x60, 0x00, 0x80, 0x3d], "str q0, [x3]"), ([0x61, 0x00, 0x80, 0x3d], "str q1, [x3]"), @@ -2855,14 +2855,14 @@ fn test_openblas_simd_loadstore() { ([0xe0, 0x01, 0x80, 0x3d], "str q0, [x15]"), ([0xe3, 0x01, 0x80, 0x3d], "str q3, [x15]"), ([0x00, 0x02, 0x80, 0x3d], "str q0, [x16]"), - ([0xe0, 0x27, 0x80, 0x3d], "str q0, [sp, 144]"), - ([0xe1, 0x2b, 0x80, 0x3d], "str q1, [sp, 160]"), - ([0xe2, 0x2f, 0x80, 0x3d], "str q2, [sp, 176]"), - ([0xe3, 0x33, 0x80, 0x3d], "str q3, [sp, 192]"), - ([0xe4, 0x37, 0x80, 0x3d], "str q4, [sp, 208]"), - ([0xe5, 0x3b, 0x80, 0x3d], "str q5, [sp, 224]"), - ([0xe6, 0x3f, 0x80, 0x3d], "str q6, [sp, 240]"), - ([0xe7, 0x43, 0x80, 0x3d], "str q7, [sp, 256]"), + ([0xe0, 0x27, 0x80, 0x3d], "str q0, [sp, 0x90]"), + ([0xe1, 0x2b, 0x80, 0x3d], "str q1, [sp, 0xa0]"), + ([0xe2, 0x2f, 0x80, 0x3d], "str q2, [sp, 0xb0]"), + ([0xe3, 0x33, 0x80, 0x3d], "str q3, [sp, 0xc0]"), + ([0xe4, 0x37, 0x80, 0x3d], "str q4, [sp, 0xd0]"), + ([0xe5, 0x3b, 0x80, 0x3d], "str q5, [sp, 0xe0]"), + ([0xe6, 0x3f, 0x80, 0x3d], "str q6, [sp, 0xf0]"), + ([0xe7, 0x43, 0x80, 0x3d], "str q7, [sp, 0x100]"), ([0x20, 0x00, 0xc0, 0x3d], "ldr q0, [x1]"), ([0x21, 0x00, 0xc0, 0x3d], "ldr q1, [x1]"), ([0x24, 0x00, 0xc0, 0x3d], "ldr q4, [x1]"), @@ -2878,33 +2878,33 @@ fn test_openblas_simd_loadstore() { ([0x44, 0x01, 0xc0, 0x3d], "ldr q4, [x10]"), ([0xc1, 0x05, 0xc0, 0x3d], "ldr q1, [x14, 0x10]"), ([0xe5, 0x05, 0xc0, 0x3d], "ldr q5, [x15, 0x10]"), - ([0xc2, 0x09, 0xc0, 0x3d], "ldr q2, [x14, 32]"), - ([0xe6, 0x09, 0xc0, 0x3d], "ldr q6, [x15, 32]"), + ([0xc2, 0x09, 0xc0, 0x3d], "ldr q2, [x14, 0x20]"), + ([0xe6, 0x09, 0xc0, 0x3d], "ldr q6, [x15, 0x20]"), ([0x33, 0x0c, 0xc0, 0x3d], "ldr q19, [x1, 0x30]"), ([0x85, 0x0c, 0xc0, 0x3d], "ldr q5, [x4, 0x30]"), ([0x83, 0x0d, 0xc0, 0x3d], "ldr q3, [x12, 0x30]"), ([0xa7, 0x0d, 0xc0, 0x3d], "ldr q7, [x13, 0x30]"), ([0xc3, 0x0d, 0xc0, 0x3d], "ldr q3, [x14, 0x30]"), ([0xe7, 0x0d, 0xc0, 0x3d], "ldr q7, [x15, 0x30]"), - ([0x00, 0x06, 0xc1, 0xac], "ldp q0, q1, [x16], 32"), - ([0xbe, 0x7d, 0xc1, 0xac], "ldp q30, q31, [x13], 32"), + ([0x00, 0x06, 0xc1, 0xac], "ldp q0, q1, [x16], 0x20"), + ([0xbe, 0x7d, 0xc1, 0xac], "ldp q30, q31, [x13], 0x20"), ([0xb0, 0x44, 0x00, 0xad], "stp q16, q17, [x5]"), - ([0x82, 0x0d, 0x01, 0xad], "stp q2, q3, [x12, 32]"), - ([0xc2, 0x0d, 0x01, 0xad], "stp q2, q3, [x14, 32]"), - ([0xb8, 0x64, 0x02, 0xad], "stp q24, q25, [x5, 64]"), - ([0xba, 0x6c, 0x03, 0xad], "stp q26, q27, [x5, 96]"), + ([0x82, 0x0d, 0x01, 0xad], "stp q2, q3, [x12, 0x20]"), + ([0xc2, 0x0d, 0x01, 0xad], "stp q2, q3, [x14, 0x20]"), + ([0xb8, 0x64, 0x02, 0xad], "stp q24, q25, [x5, 0x40]"), + ([0xba, 0x6c, 0x03, 0xad], "stp q26, q27, [x5, 0x60]"), ([0xc0, 0x04, 0x40, 0xad], "ldp q0, q1, [x6]"), ([0xb0, 0x44, 0x40, 0xad], "ldp q16, q17, [x5]"), - ([0x02, 0x0e, 0x41, 0xad], "ldp q2, q3, [x16, 32]"), - ([0x68, 0x25, 0x41, 0xad], "ldp q8, q9, [x11, 32]"), - ([0x6c, 0x35, 0x41, 0xad], "ldp q12, q13, [x11, 32]"), - ([0x7c, 0x74, 0x42, 0xad], "ldp q28, q29, [x3, 64]"), - ([0x02, 0x0e, 0x43, 0xad], "ldp q2, q3, [x16, 96]"), - ([0x06, 0x1e, 0x43, 0xad], "ldp q6, q7, [x16, 96]"), - ([0x30, 0x44, 0x43, 0xad], "ldp q16, q17, [x1, 96]"), - ([0x3e, 0x7c, 0x47, 0xad], "ldp q30, q31, [x1, 224]"), + ([0x02, 0x0e, 0x41, 0xad], "ldp q2, q3, [x16, 0x20]"), + ([0x68, 0x25, 0x41, 0xad], "ldp q8, q9, [x11, 0x20]"), + ([0x6c, 0x35, 0x41, 0xad], "ldp q12, q13, [x11, 0x20]"), + ([0x7c, 0x74, 0x42, 0xad], "ldp q28, q29, [x3, 0x40]"), + ([0x02, 0x0e, 0x43, 0xad], "ldp q2, q3, [x16, 0x60]"), + ([0x06, 0x1e, 0x43, 0xad], "ldp q6, q7, [x16, 0x60]"), + ([0x30, 0x44, 0x43, 0xad], "ldp q16, q17, [x1, 0x60]"), + ([0x3e, 0x7c, 0x47, 0xad], "ldp q30, q31, [x1, 0xe0]"), ([0x6e, 0x3d, 0xc1, 0x6c], "ldp d14, d15, [x11], 0x10"), - ([0xe8, 0x27, 0xc4, 0x6c], "ldp d8, d9, [sp], 64"), + ([0xe8, 0x27, 0xc4, 0x6c], "ldp d8, d9, [sp], 0x40"), ([0x81, 0x01, 0x00, 0x6d], "stp d1, d0, [x12]"), ([0x39, 0x60, 0x00, 0x6d], "stp d25, d24, [x1]"), ([0xdd, 0x71, 0x01, 0x6d], "stp d29, d28, [x14, 0x10]"), @@ -2937,13 +2937,13 @@ fn test_openblas_simd_loadstore() { ([0x22, 0x6b, 0x78, 0xfc], "ldr d2, [x25, x24]"), ([0x08, 0x78, 0x78, 0xfc], "ldr d8, [x0, x24, lsl 3]"), ([0xf3, 0x9b, 0x41, 0xfd], "ldr d19, [sp, 0x330]"), - ([0x4a, 0x44, 0x47, 0xfd], "ldr d10, [x2, 3720]"), - ([0x01, 0xd0, 0x47, 0xfd], "ldr d1, [x0, 4000]"), + ([0x4a, 0x44, 0x47, 0xfd], "ldr d10, [x2, 0xe88]"), + ([0x01, 0xd0, 0x47, 0xfd], "ldr d1, [x0, 0xfa0]"), ([0xe8, 0x27, 0xbc, 0x6d], "stp d8, d9, [sp, -0x40]!"), ([0xe8, 0x27, 0xbf, 0x6d], "stp d8, d9, [sp, -0x10]!"), - ([0xa2, 0x0f, 0x32, 0x3d], "str b2, [x29, 3203]"), - ([0x97, 0xff, 0xff, 0x1c], "ldr s23, 8b95f8 <zscal_k_TSV110@@Base+0x10>"), - ([0x6e, 0x3d, 0xc1, 0x2c], "ldp s14, s15, [x11], 8"), + ([0xa2, 0x0f, 0x32, 0x3d], "str b2, [x29, 0xc83]"), + ([0x97, 0xff, 0xff, 0x1c], "ldr s23, $-0x10"), + ([0x6e, 0x3d, 0xc1, 0x2c], "ldp s14, s15, [x11], 0x8"), ([0xef, 0x7e, 0x40, 0x2d], "ldp s15, s31, [x23]"), ([0x41, 0x80, 0x40, 0x2d], "ldp s1, s0, [x2, 0x4]"), ([0x33, 0xd0, 0x7f, 0x2d], "ldp s19, s20, [x1, -0x4]"), @@ -2964,8 +2964,8 @@ fn test_openblas_simd_loadstore() { ([0x88, 0x7b, 0x21, 0xbc], "str s8, [x28, x1, lsl 2]"), ([0x60, 0xda, 0x21, 0xbc], "str s0, [x19, w1, sxtw 2]"), ([0xc0, 0x5a, 0x32, 0xbc], "str s0, [x22, w18, uxtw 2]"), - ([0xb3, 0x85, 0x40, 0xbc], "ldr s19, [x13], 8"), - ([0x02, 0x8f, 0x40, 0xbc], "ldr s2, [x24, 8]!"), + ([0xb3, 0x85, 0x40, 0xbc], "ldr s19, [x13], 0x8"), + ([0x02, 0x8f, 0x40, 0xbc], "ldr s2, [x24, 0x8]!"), ([0x71, 0x05, 0x41, 0xbc], "ldr s17, [x11], 0x10"), ([0xe0, 0x42, 0x5d, 0xbc], "ldur s0, [x23, -0x2c]"), ([0x27, 0x80, 0x5d, 0xbc], "ldur s7, [x1, -0x28]"), @@ -2980,10 +2980,10 @@ fn test_openblas_simd_loadstore() { ([0x49, 0x03, 0x00, 0xbd], "str s9, [x26]"), ([0x62, 0x78, 0x00, 0xbd], "str s2, [x3, 0x78]"), ([0x6c, 0x78, 0x00, 0xbd], "str s12, [x3, 0x78]"), - ([0xea, 0x7f, 0x00, 0xbd], "str s10, [sp, 124]"), - ([0xe9, 0x87, 0x04, 0xbd], "str s9, [sp, 1156]"), - ([0xc0, 0x8a, 0x0a, 0xbd], "str s0, [x22, 2696]"), - ([0x41, 0x58, 0x4f, 0xbd], "ldr s1, [x2, 3928]"), + ([0xea, 0x7f, 0x00, 0xbd], "str s10, [sp, 0x7c]"), + ([0xe9, 0x87, 0x04, 0xbd], "str s9, [sp, 0x484]"), + ([0xc0, 0x8a, 0x0a, 0xbd], "str s0, [x22, 0xa88]"), + ([0x41, 0x58, 0x4f, 0xbd], "ldr s1, [x2, 0xf58]"), ([0x88, 0x7c, 0x00, 0x2d], "stp s8, s31, [x4]"), ([0x03, 0x84, 0x00, 0x2d], "stp s3, s1, [x0, 0x4]"), ([0x13, 0xdc, 0x3f, 0x2d], "stp s19, s23, [x0, -0x4]"), @@ -4109,8 +4109,8 @@ fn test_openblas_simd_ops() { ([0x7b, 0x1f, 0x3b, 0x6e], "eor v27.16b, v27.16b, v27.16b"), ([0xbd, 0x1f, 0x3d, 0x6e], "eor v29.16b, v29.16b, v29.16b"), ([0xff, 0x1f, 0x3f, 0x6e], "eor v31.16b, v31.16b, v31.16b"), - ([0xa5, 0x40, 0x05, 0x6e], "ext v5.16b, v5.16b, v5.16b, 8"), - ([0xc7, 0x40, 0x06, 0x6e], "ext v7.16b, v6.16b, v6.16b, 8"), + ([0xa5, 0x40, 0x05, 0x6e], "ext v5.16b, v5.16b, v5.16b, 0x8"), + ([0xc7, 0x40, 0x06, 0x6e], "ext v7.16b, v6.16b, v6.16b, 0x8"), ([0x02, 0x1d, 0x21, 0x0e], "and v2.8b, v8.8b, v1.8b"), ([0x21, 0x1c, 0x22, 0x0e], "and v1.8b, v1.8b, v2.8b"), ([0x21, 0x1c, 0x32, 0x0e], "and v1.8b, v1.8b, v18.8b"), |