Age | Commit message (Collapse) | Author |
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in addition to the decoding support, objdump reporting of `{}` selection
of multiple registers seems to be inconsistent. stick to the manual's
preferred `{v1, v2, v3, v4}` nomenclature instead of `{v1-v4}`.
reorder a few tests in test_openblas_simd_loadstore to group
instructions by decode category
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the comment was even correct! but the actual check was not.
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extended register forms of ld*/st* instructions do not shift by 0 or 1,
they are an instruction/operand-size-dependent shift amount.
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in fact the decoder should _never_ panic. included here are tests that
cover the entire 32-bit instruction space and ensure that decoding and
display do not panic. these tests run uncomfortably slowly (1168s to
decode the 4b "instruction" sequences on my desktop), but verify that
panics are no longer an issue.
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