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2021-12-29tweaks to match reference shift displayiximeow
2021-12-29more armv8.1 instructions, fix cas operand checkiximeow
2021-12-29and sve should error for nowiximeow
2021-12-29stxrb memory operand erroriximeow
2021-12-29write immediates in arm-styleiximeow
2021-12-29cas and sme/sve stubiximeow
2021-12-29clean up warnings, several of which were real bugsiximeow
2021-12-29impl Display for opcode, move lots out of Instructioniximeow
2021-12-28re-enable exhaustive panic testsiximeow
2021-12-28cleanupiximeow
2021-12-28correct some invalid tables, handle invalid opcodesiximeow
2021-12-28sys and sysliximeow
2021-12-28handle a few more invalid instructionsiximeow
2021-12-28{s,u,}bfm error case handlingiximeow
2021-12-28simd modified immediate expansioniximeow
2021-12-28armv8.1 atomic opsiximeow
2021-12-27fix variable-width index, more fp16 instructionsiximeow
2021-12-27crypto instructions and paciximeow
2021-12-27that decode arm is already handlediximeow
2021-12-27confused scalar and non-scalar simd tablesiximeow
2021-12-27another form of prfmiximeow
2021-12-27fix barriersiximeow
2021-12-27msriximeow
2021-12-27mrsiximeow
2021-12-27prfmiximeow
2021-12-27Advanced SIMD scalar pairwiseiximeow
2021-12-27movi/mvni scalar/vectoriximeow
2021-12-27fcmp/fcmpe fixesiximeow
2021-12-27missing Advanced SIMD Three Same instructionsiximeow
2021-12-27vector fabs/fcm*iximeow
2021-12-27vector x indexed fmla,fmls,fmuliximeow
2021-12-27Advanced SIMD Extractiximeow
2021-12-27fix Advanced SIMD Scalar Three Sameiximeow
2021-12-27more tests that were inaccurateiximeow
2021-12-27significantly expand simd support, correct tests for aliasingiximeow
2021-12-17expand scalar supportneoniximeow
2021-12-04ignore non-panic tests for nowiximeow
2021-12-04significant progress towards the rest of simdiximeow
2021-11-20quiet some warningsiximeow
2021-11-20more simd supportiximeow
2021-11-07floating point mov, several data processing ops, compareiximeow
2021-10-31SIMD load/store (multiple structure)iximeow
in addition to the decoding support, objdump reporting of `{}` selection of multiple registers seems to be inconsistent. stick to the manual's preferred `{v1, v2, v3, v4}` nomenclature instead of `{v1-v4}`. reorder a few tests in test_openblas_simd_loadstore to group instructions by decode category
2021-10-31mechanical transform to avoid risk of panicking indexiximeow
2021-10-30support ldp/stp/others, preindex writeback is optionaliximeow
2021-10-30support simd load/store (single structure)iximeow
2021-10-26add many test cases from openblas, ldnp, stnpiximeow
2021-10-26ldrsw, correct some bitmasks, more ld/stiximeow
2021-10-26ubfm/sbfm aliasesiximeow
2021-10-26extriximeow
2021-10-26data processing (2 source)iximeow
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