yaxpeax-arm - yaxpeax arm decoder

Age	Commit message (Collapse)	Author
70 min.	0.5.0HEAD 0.5.0 no-gods-no-	iximeow

87 min.	fix some lingering warnings	iximeow

92 min.	that case is not unpredictable anymore!	iximeow

94 min.	immediate consistency across the library	iximeow

94 min.	report rounding bit of smmla/smmls	iximeow

2 hours	fix hvc immediate missing its upper four bits	iximeow

2 hours	fix ssat/16 second operand off by one, testcases	iximeow

2 hours	fix issues around unpredictable ldrd and offset printing	iximeow

2 hours	fix {s,u}xt{h,b}[16] using an immediate to describe their rotates	iximeow

2 hours	fix mrc/mrc2 use of CRd=15	iximeow

2 hours	thumb differential test must handle shift descriptions, other refinements	iximeow

2 hours	more lining up differential tests	iximeow

2026-08-06	cdp/mrc/mcr opc1 is wider than display knows	iximeow
	i think this is fixing an issue that was introduced in the diff between 0.4.0 and 0.5.0, so it's elided from the changelog..
2026-08-04	write condition code before .w suffix	iximeow

2026-08-04	more leftover capstone cs_insn reuse stuff	iximeow

2026-08-04	msr confusion like with mrs..	iximeow

2026-08-03	use cs_disasm() to stop inheriting bogus cc state	iximeow

2026-08-03	armv8 thumb-mode hints	iximeow

2026-08-03	wip differential support (differences mostly understood)	iximeow
	of course, all the TODOs need to stop existing
2026-08-03	decode unknown wide hints like any other hints	iximeow

2026-08-03	thumb differential: much more reasonable operand parsing for memory ops..	iximeow

2026-08-02	fix swapped rfe{ia,db} and srs{ia,db}	iximeow

2026-08-02	fix missing decode of `s` bit for wide shift/rotate ops	iximeow

2026-08-02	thumb ldc/stc encodings missed a bit	iximeow

2026-08-02	sufficiently advanced SIMD is indistinguishable from coprocessors	iximeow

2026-08-02	thumb2 preload improvements	iximeow

2026-08-02	thumb SIMD encoding should have returned Incomplete	iximeow

2026-08-02	pkhbt/pkhtb bitmask confusion	iximeow

2026-08-02	Test Target, fix bogus MRS destinations	iximeow

2026-08-02	ldrexd changelog	iximeow

2026-08-02	thumb mrs/msr first operand was wildly wrong	iximeow

2026-07-28	temp, armv8-thumb	iximeow

2026-07-28	thumb2: fix parallel addition/subtraction, (un)signed	iximeow

2026-07-28	thumb: when nonconforming, allow it/cond=1111 like capstone	iximeow

2026-07-28	thumb differential: segment out a few categories of diff	iximeow

2026-07-28	capstone prints thumb add/sub sp+immediate as two operands	iximeow

2026-07-28	differential test should tolerate a few more differences	iximeow

2026-07-28	untangle some nonconforming ld/st forms	iximeow

2026-07-28	lsl/mov aliasing	iximeow

2026-07-28	differential testing wip	iximeow

2026-07-28	fix thumb2 TBH decode: wrong opcode and register-shift operand	Brandon Ros
	the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the index operand with bit 4 set in the RegShift raw value. bit 4 is the RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it reads back as the RegImm 'lsl #1' the encoding specifies. verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1].
2026-07-28	fix more thumb2 register data-processing decode bugs	Brandon Ros
	- register-controlled shifts (lsl/lsr/asr/ror by register) all decoded as lsl: the shift type was read from hw1[6:5] (always 0 for this form) instead of hw0[6:5] - 32-bit uxt/sxt extends read the ror amount from the wrong field (hw1[2:1] scaled by 4 instead of hw1[5:4] scaled by 8), so a no-rotation extend came back as ror #4; rotation of 0 is now omitted - sxtab was decoded as sxtah (wrong opcode table entry) all cases verified against binutils objdump
2026-07-28	some armv7/thumb arms are basically duplicate	iximeow

2026-07-28	fix several thumb2 decode bugs	Brandon Ros
	- 32-bit store encodings with the imm12 bit (bit 23) set were decoded as the register-offset form when imm12 < 64, or as strbt/strht/strt when imm12 was 0xExx. bit 23 set always means the imm12 form. - movw/movt packed imm4 at bit 16 instead of bit 12, producing 20-bit immediates (e.g. 0xf0005 instead of 0xf005) - mvn (immediate) was decoded as mov, dropping the bitwise not - ror (immediate) was decoded as asr all cases verified against binutils objdump
2026-07-28	Do not add an 's' when outputing opcodes that always set flags	Grond

2026-07-28	Decode the correct number of operands for TST/TEQ (immediate/register)	Grond

2026-07-28	Simplify decoding of register-shifted-register data-processing instructions	Grond
	Previously, immediate-shifted-register and register-shifted-register data-processing instructions were decoded using separate decoding paths, which caused extra complexity. These two forms differ only in the interpretation of their shifting constructs, which is already handled through the `RegShift` type. This change also fixes instructions like `cmp r0, r1, lsl r2` from being decoded with an extra operand.
2026-07-28	probably should decide where imm-shifted reg normalization happens	iximeow

2026-07-28	Decode the correct number of operands for CMP/CMN (immediate/register)	Grond
	This also incidentally fixes an issue where MOV/MVN instructions with a shifted operand could be decoded as if they had 3 operands.
2026-07-28	Fix the handling of reserved bits in uncommon loads/stores	Grond
	There's a pattern of load/store instructions that look something like * `ldr<variant> <target registers>, [<base register>, +/- <offset register>]` * `str<variant> <target registers>, [<base register>, +/- <offset register>]` These instructions share a common encoding format, which includes the presence of 4 reserved bits starting at bit 8 in the instruction word. These bits should always be zero, according to `DDI0406C_d_armv7ar_arm.pdf`. However, while this crate did attempt to validate these bits sometimes, the validation was inverted. Instead of checking that the bits were zero, the validation would raise an error if all of the bits were zero! Additionally, some instructions were missing the check and some instructions that did not use the aforementioned encoding scheme incorrectly had the check applied to them. This commit fixes all of the issues I've found along these lines so far.