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18 hoursadjust goodfile to exercise feature matrix moreiximeow
18 hoursalloc needs yaxpeax-arch alloc tooiximeow
18 hoursRemove empty format precision specifierMarijn Schouten
A format precision specifier consisting of a dot and no number actually does nothing and has no specified meaning. Currently this is silently ignored, but it may turn into a warning or error. See rust-lang/rust#131159 and rust-lang/rust#136638
18 hoursupdate changelog, no 0.3.2 after alliximeow
18 hoursOpcode and Operand should be non-exhaustiveiximeow
but exhaustiveness checking is very valuable here, so allow it to be disabled. caveats apply. read the docs in Cargo.toml.
18 hoursavoid subtle changes to A64 Opcode enum discriminant choicesiximeow
18 hourstag instruction decode fixes, differential test precisioniximeow
18 hoursfix opcode display for ldgMartin Fink
18 hoursvisitor-oriented fmtiximeow
this makes a decode+format benchmark drop from 75s to 14s... (decode is 5s)
2025-06-20changelog + another inlineiximeow
2025-06-02some armv7 decode helpers are trivial functions but didn't inlineiximeow
both from_u8 and the build function here compiled to truly trivial code: four instructions (mov rdi, rax; cmp 0xlim, rax; jae panic; ret) in the hot path, and constrained register choice on the caller side. inlining these makes for a *smaller* armv7 decoder, on the order of 5kb down from 5.5kb. in the process it also gets about 45% faster (400mb/s to 560mb/s) inlining decode_into, then, really just helps the standalone decoder benchmark case. this moves decode throughput from 560mb/s to 724mb/s.
2025-05-25support the rest of PAC instructions. compare to a more recent capstoneiximeow
capstone-rs currently binds an old capstone (4.0), where capstone 5.0 is where much of the armv8.2+ implementation was ported over from LLVM. so, differential testing is now pointed to a capstone-rs fork pending the merge of https://github.com/capstone-rust/capstone-rs/pull/172
2025-02-060.3.10.3.1iximeow
2025-02-06actually check no-std configuration does not transitively depend on stdiximeow
2025-02-04Disable bitvec features to fix no_stdLuke Street
2024-06-25update yaxpeax-arch in differential-tests, validate in goodfileiximeow
2024-06-250.3.00.3.0iximeow
2024-06-25Bump yaxpeax-arch and bitvec, allow use of deprecated yaxpeax-arch traits, ↵novafacing
fix bitvec syntax changes
2024-06-250.2.60.2.6iximeow
2024-06-25include udf note in changelogiximeow
2024-06-25Add support for `udf`Martin Fink
2024-03-17at least armv7t doesnt panic now, but im very uncertain these are rightiximeow
2024-03-17run non-panicking tests with a horkton of parallelismiximeow
they run in minute or so now and the thumb mode panics....???
2024-03-17armv8 no-panic test is now multithreadediximeow
2024-03-17differential test: more refinement on exceptionsiximeow
2024-03-17resolve warnings, make textual disassembly in differential tests a little fasteriximeow
2024-03-17differential tests: RUSTFLAGS on aarch64 noteiximeow
2024-03-17ye olde "const array rebuilt in locals with simd but static is const" issueiximeow
2024-03-17differential tests: unnecessary mutiximeow
2024-03-17ah uxtw/h fix introduced warningsiximeow
2024-03-17differential test: use raw capstone interface to avoid reallocating cs_insniximeow
2024-03-17differential test: atomic adds are relaxed, dont need specific orderingiximeow
2024-03-17fix uxtb/uxth alias being incorrectly applied with x-size registersiximeow
2024-03-17differential tests: more unneeded special casesiximeow
2024-03-17differential tests: width-aware immediate parsingiximeow
2024-03-17when decoding invalid opcodes, return errors. better testing for this ↵iximeow
circumstance.
2024-03-17disassembling sb is fine, tests ensure it happens nowiximeow
2024-03-17capstone also reports msr for some undefined encodingsiximeow
2024-03-17differential test: remove many exceptions, refine mrs exceptioniximeow
2024-03-17be more explicit about undefined system instructions being invalidiximeow
2024-03-17system instruction and register improvementsiximeow
* cN instead of crN for control registers * # for immediates in sys/sysl instructions * write out ARM system register names in the way the ARM reference manual says
2024-03-16ldrab and ldraa tests, fix immediate decodingiximeow
2024-03-16test dmb and make immediates shown with the immediate prefixiximeow
2024-03-16differential testing: parse memory operands more preciselyiximeow
to support more 0x prefix handling, since yax prints offsets with 0x even if the offset is less than 10
2024-03-16fix movi (immediate) to unpack immediate correctlyiximeow
.... and add tests that exercise movi with an immediate other than 0
2024-03-16multithread differential disassembly and support pc-relative operands, ↵iximeow
remove a few more exceptions
2024-03-16fix ldrsw register sizeiximeow
also unignore tests that would have caught this fix test expectation that predated using pc-relative syntax and fix a test that expected an instruction to be disassembled as "invalid" successfully, rather than returning an error
2024-03-14fix up differential fuzzer to rectify hex vs decimal literals in different ↵iximeow
disassemblers sure does include a quasi aarch64-asm-parser
2024-03-090.2.50.2.5iximeow
2024-03-09add goodfile for ci purposesiximeow