| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2 hours | report rounding bit of smmla/smmls | iximeow | |
| 3 hours | fix {s,u}xt{h,b}[16] using an immediate to describe their rotates | iximeow | |
| 3 hours | fix mrc/mrc2 use of CRd=15 | iximeow | |
| 2026-08-03 | armv8 thumb-mode hints | iximeow | |
| 2026-08-03 | decode unknown wide hints like any other hints | iximeow | |
| 2026-08-02 | Test Target, fix bogus MRS destinations | iximeow | |
| 2026-07-28 | temp, armv8-thumb | iximeow | |
| 2026-07-28 | differential testing wip | iximeow | |
| 2026-07-28 | Decode the correct number of operands for TST/TEQ (immediate/register) | Grond | |
| 2026-07-28 | Simplify decoding of register-shifted-register data-processing instructions | Grond | |
| Previously, immediate-shifted-register and register-shifted-register data-processing instructions were decoded using separate decoding paths, which caused extra complexity. These two forms differ only in the interpretation of their shifting constructs, which is already handled through the `RegShift` type. This change also fixes instructions like `cmp r0, r1, lsl r2` from being decoded with an extra operand. | |||
| 2026-07-28 | probably should decide where imm-shifted reg normalization happens | iximeow | |
| 2026-07-28 | Decode the correct number of operands for CMP/CMN (immediate/register) | Grond | |
| This also incidentally fixes an issue where MOV/MVN instructions with a shifted operand could be decoded as if they had 3 operands. | |||
| 2026-07-28 | Fix the handling of reserved bits in uncommon loads/stores | Grond | |
| There's a pattern of load/store instructions that look something like * `ldr<variant> <target registers>, [<base register>, +/- <offset register>]` * `str<variant> <target registers>, [<base register>, +/- <offset register>]` These instructions share a common encoding format, which includes the presence of 4 reserved bits starting at bit 8 in the instruction word. These bits should always be zero, according to `DDI0406C_d_armv7ar_arm.pdf`. However, while this crate did attempt to validate these bits sometimes, the validation was inverted. Instead of checking that the bits were zero, the validation would raise an error if all of the bits were zero! Additionally, some instructions were missing the check and some instructions that did not use the aforementioned encoding scheme incorrectly had the check applied to them. This commit fixes all of the issues I've found along these lines so far. | |||
| 2026-07-28 | Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2 | Grond | |
| 2026-07-28 | Implement the RRX immediate shift type | Grond | |
| 2026-07-28 | Fix the handling of arithmetic register shifts with zero immediates | Grond | |
| 2026-06-19 | Add armv7::InstDecoder::in_thumb_mode() method | Samuel Arnold | |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 | |
| initially was "implement MCR/MRC decoding", but expanded to include the whole coprocessor space for completeness, and then SVC is right there too. Neon instructions in this space are still rejected, as neon support is not really there yet. Co-authored-by: iximeow <me@iximeow.net> | |||
| 2026-02-22 | rename MCR2/MRC2 to MCR/MRC | rva3 | |
| they share exactly the same encoding, except the high bits for condition the bool indicates if it's A2 encondings which is unconditional | |||
| 2026-02-22 | derive Clone and Copy for armv7 instruction | rva3 | |
| 2025-10-19 | Opcode and Operand should be non-exhaustive | iximeow | |
| but exhaustiveness checking is very valuable here, so allow it to be disabled. caveats apply. read the docs in Cargo.toml. | |||
| 2025-10-19 | visitor-oriented fmt | iximeow | |
| this makes a decode+format benchmark drop from 75s to 14s... (decode is 5s) | |||
| 2025-06-02 | some armv7 decode helpers are trivial functions but didn't inline | iximeow | |
| both from_u8 and the build function here compiled to truly trivial code: four instructions (mov rdi, rax; cmp 0xlim, rax; jae panic; ret) in the hot path, and constrained register choice on the caller side. inlining these makes for a *smaller* armv7 decoder, on the order of 5kb down from 5.5kb. in the process it also gets about 45% faster (400mb/s to 560mb/s) inlining decode_into, then, really just helps the standalone decoder benchmark case. this moves decode throughput from 560mb/s to 724mb/s. | |||
| 2024-06-25 | Bump yaxpeax-arch and bitvec, allow use of deprecated yaxpeax-arch traits, ↵ | novafacing | |
| fix bitvec syntax changes | |||
| 2023-11-02 | ah and a doc comment for the public method0.2.4 | iximeow | |
| 2023-11-02 | make RegShift::into_shift public | wscp | |
| 2023-01-31 | fix 24-bit branch immediate decoding | jam1garner | |
| 2022-01-02 | document the crate | iximeow | |
| 2021-12-29 | clean up warnings, several of which were real bugs | iximeow | |
| 2021-09-28 | handle another unintended panic in display impl | iximeow | |
| 2021-09-28 | fix various armv8 and armv8 panics that should be Err. | iximeow | |
| in fact the decoder should _never_ panic. included here are tests that cover the entire 32-bit instruction space and ensure that decoding and display do not panic. these tests run uncomfortably slowly (1168s to decode the 4b "instruction" sequences on my desktop), but verify that panics are no longer an issue. | |||
| 2021-09-26 | fix unimplemented code paths panicking as unreachable | iximeow | |
| only in a64 decoding really; there wasn't an "Incomplete" error at the time, but now there is. | |||
| 2021-09-14 | Fix display of post-index writeback operands | Jonas Schievink | |
| 2021-07-21 | fix DecodeError impl on builds using yaxpeax-arch+std0.1.1 | iximeow | |
| 2021-07-06 | update yaxpeax_arch and bump version to 0.1.00.1.0 | iximeow | |
| 2021-05-07 | bump yaxpeax-arch to 0.0.5 to drop the termion dep0.0.7 | iximeow | |
| fix interface changes around YaxColors as well | |||
| 2020-12-06 | support CPS (change processor state) and some warming cleanup | iximeow | |
| 2020-12-06 | add ldc/sdc instructions and a slew of 32b thumb2 tests | iximeow | |
| 2020-12-06 | support more mul/div variants | iximeow | |
| 2020-12-06 | thumb parallel addition and subtraction | iximeow | |
| 2020-12-06 | fill out more missing thumb2 decoder | iximeow | |
| 2020-12-06 | fix more incomplete cases, report arm instruction length properly | iximeow | |
| 2020-12-06 | remove "Incomplete" opcode from arm7 non-thumb decoder | iximeow | |
| 2020-12-06 | fix regimm masks | iximeow | |
| 2020-12-06 | numerous one-off mis-specializations, most of ld/prefetch hints | iximeow | |
| 2020-12-06 | fix some 32-bit thumb2 instructions, hook up .w, `s`, and a few typos | iximeow | |
| mostly confusion of pre/post-increment, operand widths, immediate widths, things of that nature | |||
| 2020-12-06 | add thumb/thumb2 decoding | iximeow | |
| 16-bit instructions only, for now | |||
| 2020-11-29 | normalize stm/ldm to use RegWBack | iximeow | |
| 2020-05-03 | bump to version 0.0.4, bumping yaxpeax-arch to 0.0.40.0.4 | iximeow | |
| 2020-03-15 | clean up operands some | iximeow | |
 |
index : yaxpeax-arm | |
| yaxpeax arm decoder |
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