yaxpeax-arm - yaxpeax arm decoder

Age	Commit message (Collapse)	Author
4 hours	fix some lingering warnings	iximeow

5 hours	immediate consistency across the library	iximeow

5 hours	report rounding bit of smmla/smmls	iximeow

5 hours	fix issues around unpredictable ldrd and offset printing	iximeow

5 hours	fix {s,u}xt{h,b}[16] using an immediate to describe their rotates	iximeow

5 hours	fix mrc/mrc2 use of CRd=15	iximeow

2026-08-06	cdp/mrc/mcr opc1 is wider than display knows	iximeow
	i think this is fixing an issue that was introduced in the diff between 0.4.0 and 0.5.0, so it's elided from the changelog..
2026-08-04	write condition code before .w suffix	iximeow

2026-08-03	armv8 thumb-mode hints	iximeow

2026-08-02	Test Target, fix bogus MRS destinations	iximeow

2026-07-28	temp, armv8-thumb	iximeow

2026-07-28	thumb: when nonconforming, allow it/cond=1111 like capstone	iximeow

2026-07-28	lsl/mov aliasing	iximeow

2026-07-28	differential testing wip	iximeow

2026-07-28	Do not add an 's' when outputing opcodes that always set flags	Grond

2026-07-28	Implement the RRX immediate shift type	Grond

2026-02-22	support A1 encoding of several coprocessor instructions + SVC	rva3
	initially was "implement MCR/MRC decoding", but expanded to include the whole coprocessor space for completeness, and then SVC is right there too. Neon instructions in this space are still rejected, as neon support is not really there yet. Co-authored-by: iximeow <me@iximeow.net>
2026-02-22	properly display coprocessor higher than 9	rva3

2026-02-22	rename MCR2/MRC2 to MCR/MRC	rva3
	they share exactly the same encoding, except the high bits for condition the bool indicates if it's A2 encondings which is unconditional
2025-10-19	visitor-oriented fmt	iximeow
	this makes a decode+format benchmark drop from 75s to 14s... (decode is 5s)