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2021-12-27another form of prfmiximeow
2021-12-27fix barriersiximeow
2021-12-27msriximeow
2021-12-27mrsiximeow
2021-12-27prfmiximeow
2021-12-27Advanced SIMD scalar pairwiseiximeow
2021-12-27movi/mvni scalar/vectoriximeow
2021-12-27fcmp/fcmpe fixesiximeow
2021-12-27missing Advanced SIMD Three Same instructionsiximeow
2021-12-27vector fabs/fcm*iximeow
2021-12-27vector x indexed fmla,fmls,fmuliximeow
2021-12-27Advanced SIMD Extractiximeow
2021-12-27fix Advanced SIMD Scalar Three Sameiximeow
2021-12-27significantly expand simd support, correct tests for aliasingiximeow
2021-12-17expand scalar supportneoniximeow
2021-12-04significant progress towards the rest of simdiximeow
2021-11-20quiet some warningsiximeow
2021-11-20more simd supportiximeow
2021-11-07floating point mov, several data processing ops, compareiximeow
2021-10-31SIMD load/store (multiple structure)iximeow
in addition to the decoding support, objdump reporting of `{}` selection of multiple registers seems to be inconsistent. stick to the manual's preferred `{v1, v2, v3, v4}` nomenclature instead of `{v1-v4}`. reorder a few tests in test_openblas_simd_loadstore to group instructions by decode category
2021-10-31mechanical transform to avoid risk of panicking indexiximeow
2021-10-30support ldp/stp/others, preindex writeback is optionaliximeow
2021-10-30support simd load/store (single structure)iximeow
2021-10-26add many test cases from openblas, ldnp, stnpiximeow
2021-10-26ldrsw, correct some bitmasks, more ld/stiximeow
2021-10-26ubfm/sbfm aliasesiximeow
2021-10-26extriximeow
2021-10-26data processing (2 source)iximeow
2021-10-25madd/msub aliasesiximeow
2021-10-25csneg/csinv aliasesiximeow
2021-10-25fix size of operand for ldpswiximeow
2021-10-25fix various inaccuracies in adds/subsiximeow
2021-10-25shifted/extended add/sub is contingent on bit 21, not 17iximeow
the comment was even correct! but the actual check was not.
2021-10-25correct sbfm/bfm/ubfm and their aliasesiximeow
2021-10-24use correct bitmask to select imm6iximeow
2021-10-24constify more of ld/st code, fix incorrect shift sizeiximeow
extended register forms of ld*/st* instructions do not shift by 0 or 1, they are an instruction/operand-size-dependent shift amount.
2021-10-24unsigned immediate encodings do not have signed immediatesiximeow
2021-10-24fix incorrect sign extension for adr and adrpiximeow
2021-10-24fix sign extension errors in relative instructionsiximeow
2021-10-24normalize a bit more consistently in instruction displayiximeow
2021-10-21remaining 1-source data processing instructions are unallocatediximeow
2021-10-21fix rev/rev32iximeow
2021-10-21data processing (three source)iximeow
2021-10-21data processing instructions (one source)iximeow
2021-10-21ccm{n,p}iximeow
2021-09-28do not publish crates with compilation warnings (bump for 0.1.3 also)0.1.3iximeow
2021-09-28fix various armv8 and armv8 panics that should be Err.iximeow
in fact the decoder should _never_ panic. included here are tests that cover the entire 32-bit instruction space and ensure that decoding and display do not panic. these tests run uncomfortably slowly (1168s to decode the 4b "instruction" sequences on my desktop), but verify that panics are no longer an issue.
2021-09-26fix unimplemented code paths panicking as unreachableiximeow
only in a64 decoding really; there wasn't an "Incomplete" error at the time, but now there is.
2021-07-21fix DecodeError impl on builds using yaxpeax-arch+std0.1.1iximeow
2021-07-06update yaxpeax_arch and bump version to 0.1.00.1.0iximeow
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