| Age | Commit message (Collapse) | Author |
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the comment was even correct! but the actual check was not.
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extended register forms of ld*/st* instructions do not shift by 0 or 1,
they are an instruction/operand-size-dependent shift amount.
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in fact the decoder should _never_ panic. included here are tests that
cover the entire 32-bit instruction space and ensure that decoding and
display do not panic. these tests run uncomfortably slowly (1168s to
decode the 4b "instruction" sequences on my desktop), but verify that
panics are no longer an issue.
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only in a64 decoding really; there wasn't an "Incomplete" error at the time, but now there is.
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fix interface changes around YaxColors as well
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instead of trying to shoehorn in `adr reg, label` syntax like the manual
requests, it's much easier to just describe these as `{add, sub} reg,
pc, offset` and potentially rewrite `pc, offset` as an `adr reg, label`
if a higher-level tool has that kind of information available.
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add in some simd tests for future neon decoding. these tests are drawn
from capstone and may need some subsequent cleanup
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mostly confusion of pre/post-increment, operand widths, immediate
widths, things of that nature
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16-bit instructions only, for now
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