| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 21 hours | Opcode and Operand should be non-exhaustive | iximeow | |
| but exhaustiveness checking is very valuable here, so allow it to be disabled. caveats apply. read the docs in Cargo.toml. | |||
| 21 hours | avoid subtle changes to A64 Opcode enum discriminant choices | iximeow | |
| 21 hours | tag instruction decode fixes, differential test precision | iximeow | |
| 21 hours | fix opcode display for ldg | Martin Fink | |
| 21 hours | visitor-oriented fmt | iximeow | |
| this makes a decode+format benchmark drop from 75s to 14s... (decode is 5s) | |||
| 2025-06-20 | changelog + another inline | iximeow | |
| 2025-06-02 | some armv7 decode helpers are trivial functions but didn't inline | iximeow | |
| both from_u8 and the build function here compiled to truly trivial code: four instructions (mov rdi, rax; cmp 0xlim, rax; jae panic; ret) in the hot path, and constrained register choice on the caller side. inlining these makes for a *smaller* armv7 decoder, on the order of 5kb down from 5.5kb. in the process it also gets about 45% faster (400mb/s to 560mb/s) inlining decode_into, then, really just helps the standalone decoder benchmark case. this moves decode throughput from 560mb/s to 724mb/s. | |||
| 2025-05-25 | support the rest of PAC instructions. compare to a more recent capstone | iximeow | |
| capstone-rs currently binds an old capstone (4.0), where capstone 5.0 is where much of the armv8.2+ implementation was ported over from LLVM. so, differential testing is now pointed to a capstone-rs fork pending the merge of https://github.com/capstone-rust/capstone-rs/pull/172 | |||
| 2024-06-25 | Bump yaxpeax-arch and bitvec, allow use of deprecated yaxpeax-arch traits, ↵ | novafacing | |
| fix bitvec syntax changes | |||
| 2024-06-25 | Add support for `udf` | Martin Fink | |
| 2024-03-17 | at least armv7t doesnt panic now, but im very uncertain these are right | iximeow | |
| 2024-03-17 | ye olde "const array rebuilt in locals with simd but static is const" issue | iximeow | |
| 2024-03-17 | ah uxtw/h fix introduced warnings | iximeow | |
| 2024-03-17 | fix uxtb/uxth alias being incorrectly applied with x-size registers | iximeow | |
| 2024-03-17 | when decoding invalid opcodes, return errors. better testing for this ↵ | iximeow | |
| circumstance. | |||
| 2024-03-17 | be more explicit about undefined system instructions being invalid | iximeow | |
| 2024-03-17 | system instruction and register improvements | iximeow | |
| * cN instead of crN for control registers * # for immediates in sys/sysl instructions * write out ARM system register names in the way the ARM reference manual says | |||
| 2024-03-16 | ldrab and ldraa tests, fix immediate decoding | iximeow | |
| 2024-03-16 | test dmb and make immediates shown with the immediate prefix | iximeow | |
| 2024-03-16 | fix movi (immediate) to unpack immediate correctly | iximeow | |
| .... and add tests that exercise movi with an immediate other than 0 | |||
| 2024-03-16 | fix ldrsw register size | iximeow | |
| also unignore tests that would have caught this fix test expectation that predated using pc-relative syntax and fix a test that expected an instruction to be disassembled as "invalid" successfully, rather than returning an error | |||
| 2024-03-09 | improve msr register decoding | iximeow | |
| "improve" rather than "fix" as `pstate.0x3` is hardly as useful as `msr uao, #3`. but the "pstate field" that had been decoded before was totally incorrect. | |||
| 2024-03-09 | fix armv8 a64 decoder hint instructions | belovdv | |
| 2023-11-02 | ah and a doc comment for the public method0.2.4 | iximeow | |
| 2023-11-02 | make RegShift::into_shift public | wscp | |
| 2023-01-31 | fix 24-bit branch immediate decoding | jam1garner | |
| 2022-09-29 | Fix 32-bit conditional thumb branches | Mitchell Johnson | |
| Correct the shift used to select condition bits and correctly compute the branch offset. | |||
| 2022-09-29 | Fix negative unconditional 16-bit thumb branches | Mitchell Johnson | |
| Sign extension shift had an off-by-one error so the sign bit was not being properly extended. | |||
| 2022-09-29 | Fix 32-bit Thumb unconditional branch decoding | Mitchell Johnson | |
| T4 encodings of unconditional branches were not being interpreted correctly (#6), and 32-bit bl/blx instructions were similarly incorrect. Correct the bits selected for op1 and op2 and handle the slightly-unusual i1/i2 sign bit xor for these instructions. | |||
| 2022-04-08 | Fix no_std builds | Mitchell Johnson | |
| 2022-01-02 | fix docs that failed to build | iximeow | |
| 2022-01-02 | why did that compile | iximeow | |
| 2022-01-02 | document the crate | iximeow | |
| 2022-01-01 | capstone/yax differences, test pac more comprehensively | iximeow | |
| 2022-01-01 | fix float formatter | iximeow | |
| integer floats need a .0, the rest get default precision | |||
| 2022-01-01 | more inconvenient test case handling | iximeow | |
| 2022-01-01 | test expectation cleanup | iximeow | |
| 2022-01-01 | start getting the msr/hint situation under control | iximeow | |
| 2021-12-31 | more pac instructions, fmov fixes | iximeow | |
| 2021-12-31 | fix more invalid rejects, misdecodes, test cases | iximeow | |
| 2021-12-31 | shift/sm3ss fixes | iximeow | |
| 2021-12-31 | sshll is weird | iximeow | |
| 2021-12-31 | pac, cfi, other misc cleanup, notes and todos | iximeow | |
| 2021-12-30 | many many MORE one-off fixes from differential testing | iximeow | |
| 2021-12-29 | many incorrect decode/reject cases fixed | iximeow | |
| 2021-12-29 | ldapr/stlr (unscaled immediate) | iximeow | |
| 2021-12-29 | memory tags | iximeow | |
| 2021-12-29 | more missed tables and manual compat | iximeow | |
| 2021-12-29 | more misc fixes | iximeow | |
| 2021-12-29 | simd table lookup | iximeow | |
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index : yaxpeax-arm | |
| yaxpeax arm decoder |
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