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in fact the decoder should _never_ panic. included here are tests that
cover the entire 32-bit instruction space and ensure that decoding and
display do not panic. these tests run uncomfortably slowly (1168s to
decode the 4b "instruction" sequences on my desktop), but verify that
panics are no longer an issue.
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instead of trying to shoehorn in `adr reg, label` syntax like the manual
requests, it's much easier to just describe these as `{add, sub} reg,
pc, offset` and potentially rewrite `pc, offset` as an `adr reg, label`
if a higher-level tool has that kind of information available.
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add in some simd tests for future neon decoding. these tests are drawn
from capstone and may need some subsequent cleanup
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16-bit instructions only, for now
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