| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-07-28 | Fix the handling of arithmetic register shifts with zero immediates | Grond | |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 | |
| initially was "implement MCR/MRC decoding", but expanded to include the whole coprocessor space for completeness, and then SVC is right there too. Neon instructions in this space are still rejected, as neon support is not really there yet. Co-authored-by: iximeow <me@iximeow.net> | |||
| 2026-02-22 | properly display coprocessor higher than 9 | rva3 | |
| 2023-01-31 | fix 24-bit branch immediate decoding | jam1garner | |
| 2022-01-02 | get test situation in order | iximeow | |
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index : yaxpeax-arm | |
| yaxpeax arm decoder |
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