| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 8 hours | that case is not unpredictable anymore! | iximeow | |
| 8 hours | immediate consistency across the library | iximeow | |
| 8 hours | report rounding bit of smmla/smmls | iximeow | |
| 9 hours | fix hvc immediate missing its upper four bits | iximeow | |
| 9 hours | fix ssat/16 second operand off by one, testcases | iximeow | |
| 9 hours | fix issues around unpredictable ldrd and offset printing | iximeow | |
| 9 hours | fix {s,u}xt{h,b}[16] using an immediate to describe their rotates | iximeow | |
| 9 hours | fix mrc/mrc2 use of CRd=15 | iximeow | |
| 9 hours | more lining up differential tests | iximeow | |
| 2026-08-06 | cdp/mrc/mcr opc1 is wider than display knows | iximeow | |
| i *think* this is fixing an issue that was introduced in the diff between 0.4.0 and 0.5.0, so it's elided from the changelog.. | |||
| 2026-08-04 | write condition code *before* .w suffix | iximeow | |
| 2026-08-04 | msr confusion like with mrs.. | iximeow | |
| 2026-08-03 | armv8 thumb-mode hints | iximeow | |
| 2026-08-03 | decode unknown wide hints like any other hints | iximeow | |
| 2026-08-02 | fix swapped rfe{ia,db} and srs{ia,db} | iximeow | |
| 2026-08-02 | fix missing decode of `s` bit for wide shift/rotate ops | iximeow | |
| 2026-08-02 | thumb ldc/stc encodings missed a bit | iximeow | |
| 2026-08-02 | thumb2 preload improvements | iximeow | |
| 2026-08-02 | pkhbt/pkhtb bitmask confusion | iximeow | |
| 2026-08-02 | Test Target, fix bogus MRS destinations | iximeow | |
| 2026-08-02 | thumb mrs/msr first operand was wildly wrong | iximeow | |
| 2026-07-28 | temp, armv8-thumb | iximeow | |
| 2026-07-28 | thumb2: fix parallel addition/subtraction, (un)signed | iximeow | |
| 2026-07-28 | thumb: when nonconforming, allow it/cond=1111 like capstone | iximeow | |
| 2026-07-28 | differential test should tolerate a few more differences | iximeow | |
| 2026-07-28 | lsl/mov aliasing | iximeow | |
| 2026-07-28 | fix thumb2 TBH decode: wrong opcode and register-shift operand | Brandon Ros | |
| the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the index operand with bit 4 set in the RegShift raw value. bit 4 is the RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it reads back as the RegImm 'lsl #1' the encoding specifies. verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1]. | |||
| 2026-07-28 | fix more thumb2 register data-processing decode bugs | Brandon Ros | |
| - register-controlled shifts (lsl/lsr/asr/ror by register) all decoded as lsl: the shift type was read from hw1[6:5] (always 0 for this form) instead of hw0[6:5] - 32-bit uxt*/sxt* extends read the ror amount from the wrong field (hw1[2:1] scaled by 4 instead of hw1[5:4] scaled by 8), so a no-rotation extend came back as ror #4; rotation of 0 is now omitted - sxtab was decoded as sxtah (wrong opcode table entry) all cases verified against binutils objdump | |||
| 2026-07-28 | fix several thumb2 decode bugs | Brandon Ros | |
| - 32-bit store encodings with the imm12 bit (bit 23) set were decoded as the register-offset form when imm12 < 64, or as strbt/strht/strt when imm12 was 0xExx. bit 23 set always means the imm12 form. - movw/movt packed imm4 at bit 16 instead of bit 12, producing 20-bit immediates (e.g. 0xf0005 instead of 0xf005) - mvn (immediate) was decoded as mov, dropping the bitwise not - ror (immediate) was decoded as asr all cases verified against binutils objdump | |||
| 2022-09-29 | Add a test for issue #3 | Mitchell Johnson | |
| 2022-09-29 | Add some additional 32-bit thumb branch decode test cases | Mitchell Johnson | |
| 2022-09-29 | Fix 32-bit conditional thumb branches | Mitchell Johnson | |
| Correct the shift used to select condition bits and correctly compute the branch offset. | |||
| 2022-09-29 | Fix negative unconditional 16-bit thumb branches | Mitchell Johnson | |
| Sign extension shift had an off-by-one error so the sign bit was not being properly extended. | |||
| 2022-09-29 | Fix 32-bit Thumb unconditional branch decoding | Mitchell Johnson | |
| T4 encodings of unconditional branches were not being interpreted correctly (#6), and 32-bit bl/blx instructions were similarly incorrect. Correct the bits selected for op1 and op2 and handle the slightly-unusual i1/i2 sign bit xor for these instructions. | |||
| 2022-01-02 | get test situation in order | iximeow | |
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index : yaxpeax-arm | |
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