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the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the
index operand with bit 4 set in the RegShift raw value. bit 4 is the
RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index
scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it
reads back as the RegImm 'lsl #1' the encoding specifies.
verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1].
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- register-controlled shifts (lsl/lsr/asr/ror by register) all decoded as
lsl: the shift type was read from hw1[6:5] (always 0 for this form)
instead of hw0[6:5]
- 32-bit uxt*/sxt* extends read the ror amount from the wrong field
(hw1[2:1] scaled by 4 instead of hw1[5:4] scaled by 8), so a no-rotation
extend came back as ror #4; rotation of 0 is now omitted
- sxtab was decoded as sxtah (wrong opcode table entry)
all cases verified against binutils objdump
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- 32-bit store encodings with the imm12 bit (bit 23) set were decoded as
the register-offset form when imm12 < 64, or as strbt/strht/strt when
imm12 was 0xExx. bit 23 set always means the imm12 form.
- movw/movt packed imm4 at bit 16 instead of bit 12, producing 20-bit
immediates (e.g. 0xf0005 instead of 0xf005)
- mvn (immediate) was decoded as mov, dropping the bitwise not
- ror (immediate) was decoded as asr
all cases verified against binutils objdump
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Correct the shift used to select condition bits and correctly compute the
branch offset.
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Sign extension shift had an off-by-one error so the sign bit was not being
properly extended.
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T4 encodings of unconditional branches were not being interpreted correctly
(#6), and 32-bit bl/blx instructions were similarly incorrect. Correct the bits
selected for op1 and op2 and handle the slightly-unusual i1/i2 sign bit xor for
these instructions.
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