| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-07-28 | Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2 | Grond | |
| 2026-07-28 | Implement the RRX immediate shift type | Grond | |
| 2026-07-28 | Fix the handling of arithmetic register shifts with zero immediates | Grond | |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 | |
| initially was "implement MCR/MRC decoding", but expanded to include the whole coprocessor space for completeness, and then SVC is right there too. Neon instructions in this space are still rejected, as neon support is not really there yet. Co-authored-by: iximeow <me@iximeow.net> | |||
| 2026-02-22 | properly display coprocessor higher than 9 | rva3 | |
| 2023-01-31 | fix 24-bit branch immediate decoding | jam1garner | |
| 2022-09-29 | Add a test for issue #3 | Mitchell Johnson | |
| 2022-09-29 | Add some additional 32-bit thumb branch decode test cases | Mitchell Johnson | |
| 2022-09-29 | Fix 32-bit conditional thumb branches | Mitchell Johnson | |
| Correct the shift used to select condition bits and correctly compute the branch offset. | |||
| 2022-09-29 | Fix negative unconditional 16-bit thumb branches | Mitchell Johnson | |
| Sign extension shift had an off-by-one error so the sign bit was not being properly extended. | |||
| 2022-09-29 | Fix 32-bit Thumb unconditional branch decoding | Mitchell Johnson | |
| T4 encodings of unconditional branches were not being interpreted correctly (#6), and 32-bit bl/blx instructions were similarly incorrect. Correct the bits selected for op1 and op2 and handle the slightly-unusual i1/i2 sign bit xor for these instructions. | |||
| 2022-01-02 | get test situation in order | iximeow | |
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index : yaxpeax-arm | |
| yaxpeax arm decoder |
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