| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-03-17 | when decoding invalid opcodes, return errors. better testing for this ↵ | iximeow | |
| circumstance. | |||
| 2024-03-17 | disassembling sb is fine, tests ensure it happens now | iximeow | |
| 2024-03-17 | be more explicit about undefined system instructions being invalid | iximeow | |
| 2024-03-17 | system instruction and register improvements | iximeow | |
| * cN instead of crN for control registers * # for immediates in sys/sysl instructions * write out ARM system register names in the way the ARM reference manual says | |||
| 2024-03-16 | ldrab and ldraa tests, fix immediate decoding | iximeow | |
| 2024-03-16 | test dmb and make immediates shown with the immediate prefix | iximeow | |
| 2024-03-16 | fix movi (immediate) to unpack immediate correctly | iximeow | |
| .... and add tests that exercise movi with an immediate other than 0 | |||
| 2024-03-16 | fix ldrsw register size | iximeow | |
| also unignore tests that would have caught this fix test expectation that predated using pc-relative syntax and fix a test that expected an instruction to be disassembled as "invalid" successfully, rather than returning an error | |||
| 2024-03-09 | improve msr register decoding | iximeow | |
| "improve" rather than "fix" as `pstate.0x3` is hardly as useful as `msr uao, #3`. but the "pstate field" that had been decoded before was totally incorrect. | |||
| 2024-03-09 | fix armv8 a64 decoder hint instructions | belovdv | |
| 2023-01-31 | fix 24-bit branch immediate decoding | jam1garner | |
| 2022-09-29 | Add a test for issue #3 | Mitchell Johnson | |
| 2022-09-29 | Add some additional 32-bit thumb branch decode test cases | Mitchell Johnson | |
| 2022-09-29 | Fix 32-bit conditional thumb branches | Mitchell Johnson | |
| Correct the shift used to select condition bits and correctly compute the branch offset. | |||
| 2022-09-29 | Fix negative unconditional 16-bit thumb branches | Mitchell Johnson | |
| Sign extension shift had an off-by-one error so the sign bit was not being properly extended. | |||
| 2022-09-29 | Fix 32-bit Thumb unconditional branch decoding | Mitchell Johnson | |
| T4 encodings of unconditional branches were not being interpreted correctly (#6), and 32-bit bl/blx instructions were similarly incorrect. Correct the bits selected for op1 and op2 and handle the slightly-unusual i1/i2 sign bit xor for these instructions. | |||
| 2022-04-08 | add makefile to test yaxpeax-arch with and without no-std | iximeow | |
| 2022-01-02 | get test situation in order | iximeow | |
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index : yaxpeax-arm | |
| yaxpeax arm decoder |
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