diff options
| author | iximeow <me@iximeow.net> | 2024-09-28 13:48:20 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2024-09-28 13:48:20 -0700 |
| commit | fcf7acecdc5eda92ed3c4c8d23a8a3232e1210ea (patch) | |
| tree | 295feeedb866a8595854169415f9e49ef1a5d512 | |
| parent | f2ea785e362ceb23956a73d11e29910b5e892bd2 (diff) | |
sketching things out
| -rw-r--r-- | .gitignore | 1 | ||||
| -rw-r--r-- | CHANGELOG | 3 | ||||
| -rw-r--r-- | Cargo.lock | 35 | ||||
| -rw-r--r-- | Cargo.toml | 14 | ||||
| -rw-r--r-- | LICENSE | 12 | ||||
| -rw-r--r-- | README.md | 30 | ||||
| -rw-r--r-- | notes/grouped_encodings | 1254 | ||||
| -rw-r--r-- | src/display.rs | 7 | ||||
| -rw-r--r-- | src/lib.rs | 934 |
9 files changed, 2290 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..ea8c4bf --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +/target diff --git a/CHANGELOG b/CHANGELOG new file mode 100644 index 0000000..3012e7b --- /dev/null +++ b/CHANGELOG @@ -0,0 +1,3 @@ +## 0.0.1 + +* wrote a decoder diff --git a/Cargo.lock b/Cargo.lock new file mode 100644 index 0000000..a65fde9 --- /dev/null +++ b/Cargo.lock @@ -0,0 +1,35 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 3 + +[[package]] +name = "autocfg" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa" + +[[package]] +name = "num-traits" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "39e3200413f237f41ab11ad6d161bc7239c84dcb631773ccd7de3dfe4b5c267c" +dependencies = [ + "autocfg", +] + +[[package]] +name = "yaxpeax-arch" +version = "0.3.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "36274fcc5403da2a7636ffda4d02eca12a1b2b8267b9d2e04447bd2ccfc72082" +dependencies = [ + "num-traits", +] + +[[package]] +name = "yaxpeax-hexagon" +version = "0.0.1" +dependencies = [ + "num-traits", + "yaxpeax-arch", +] diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..8298389 --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,14 @@ +[package] + +name = "yaxpeax-hexagon" +version = "0.0.1" +authors = [ "iximeow <me@iximeow.net>" ] +license = "0BSD" +repository = "http://git.iximeow.net/yaxpeax-hexagon/" +description = "Qualcomm Hexagon decoder for the yaxpeax project" +readme = "README.md" +edition = "2021" + +[dependencies] +yaxpeax-arch = { version = "0.3.1", default-features = false, features = [] } +"num-traits" = { version = "0.2", default-features = false } @@ -0,0 +1,12 @@ +Copyright (c) 2024 iximeow + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH +REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, +INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM +LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +PERFORMANCE OF THIS SOFTWARE. diff --git a/README.md b/README.md new file mode 100644 index 0000000..81f320d --- /dev/null +++ b/README.md @@ -0,0 +1,30 @@ +## yaxpeax-hexagon + +[](https://crates.io/crates/yaxpeax-hexagon) +[](https://docs.rs/yaxpeax-hexagon) + +qualcomm hexagon decoder implemented as part of the yaxpeax project, implementing traits provided by `yaxpeax-arch`. + +### features + +* `#[no_std]` +* exists (this is not the only Hexagon disassembler by any means) + +### mirrors + +the canonical copy of `yaxpeax-hexagon` is at [https://git.iximeow.net/yaxpeax-hexagon/](https://git.iximeow.net/yaxpeax-hexagon/). + +`yaxpeax-hexagon` is also mirrored on GitHub at [https://www.github.com/iximeow/yaxpeax-hexagon](https://www.github.com/iximeow/yaxpeax-hexagon). + +### see also + +* [idp\_hexagon](https://github.com/n-o-o-n/idp_hexagon): IDA pro module for hexagon. heavily derived from LLVM. +* [llvm](https://github.com/llvm/llvm-project/tree/e03f427/llvm/lib/Target/Hexagon) +* [r2hexagon](https://github.com/radareorg/r2hexagon): radare2's hexagon disassembler. generated from manuals. +* [hexag00n](https://github.com/programa-stic/hexag00n): python-based hexagon disassembler with IDA plugin +* [hexagon](https://github.com/gsmk/hexagon): another IDA pro processor module. wrapper for Sourcery CodeBench. +* [nogaxeh](https://github.com/ANSSI-FR/nogaxeh): another IDA pro processor module +* [rz-hexagon](https://github.com/rizinorg/rz-hexagon): hexagon disassembler for rizin. generated from LLVM. + +### changelog +a changelog across crate versions is maintained in the `CHANGELOG` file located in the repo, as well as [online](https://git.iximeow.net/yaxpeax-hexagon/tree/CHANGELOG). diff --git a/notes/grouped_encodings b/notes/grouped_encodings new file mode 100644 index 0000000..b029403 --- /dev/null +++ b/notes/grouped_encodings @@ -0,0 +1,1254 @@ + +A L I A S A L I A S A L I A S A L I A S A L I A S | Rd=neg(Rs) -> Rd=sub(#0,Rs) +A L I A S A L I A S A L I A S A L I A S A L I A S | Rd=zxtb(Rs) -> Rd=and(Rs,#255) + |dn + Rs |t5 + |Pn + |taken/nt +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 1 1|i i i i i i i|s s s s s| P P |i i i i i i i i i|d d d d d| Rd=add(Rs,#s16) - ALU32/slots 0 1 2 3 +|0 1 1 1|0 1 1 0 0 0 i|s s s s s| P P |i i i i i i i i i|d d d d d| Rd=and(Rs,#s10) - ALU32/slots 0 1 2 3 +|0 1 1 1|0 1 1 0 0 1 i|s s s s s| P P |i i i i i i i i i|d d d d d| Rd=sub(#s10,Rs) - ALU32/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 0 1|s s s s s| P P |0 - - - - - - - -|d d d d d| Rd=sxtb(Rs) - ALU32/slots 0 1 2 3 - SignExtend +|0 1 1 1|0 0 0 0 1 1 1|s s s s s| P P |0 - - - - - - - -|d d d d d| Rd=sxth(Rs) - ALU32/slots 0 1 2 3 - SignExtend +|0 1 1 1|0 0 0 0 1 1 0|s s s s s| P P |0 - - - - - - - -|d d d d d| Rd=zxth(Rs) - ALU32/slots 0 1 2 3 - SignExtend +|0 1 1 1|1 1 1 1 - - -|- - - - -| P P |- - - - - - - - -|- - - - -| nop - ALU32/slots 0 1 2 3 +|0 1 1 1|0 1 1 0 1 0 i|s s s s s| P P |i i i i i i i i i|d d d d d| Rd=or(Rs,#s10) - ALU32/slots 0 1 2 3 +|1 1 1 1|0 0 1 1 0 0 0|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=add(Rs,Rt) - ALU32/slots 0 1 2 3 +|1 1 1 1|0 1 1 0 0 1 0|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=add(Rs,Rt):sat - ALU32/slots 0 1 2 3 +|1 1 1 1|0 0 1 1 0 0 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=sub(Rt,Rs) - ALU32/slots 0 1 2 3 +|1 1 1 1|0 1 1 0 1 1 0|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=add(Rt,Rs):sat - ALU32/slots 0 1 2 3 +|1 1 1 1|0 0 0 1 0 0 0|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=and(Rs,Rt) - ALU32/slots 0 1 2 3 +|1 1 1 1|0 0 0 1 0 0 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=or(Rs,Rt) - ALU32/slots 0 1 2 3 +|1 1 1 1|0 0 0 1 0 1 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=xor(Rs,Rt) - ALU32/slots 0 1 2 3 +|1 1 1 1|0 0 0 1 1 0 0|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=and(Rt,~Rs) - ALU32/slots 0 1 2 3 +|1 1 1 1|0 0 0 1 1 0 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=and(Rt,~Rs) - ALU32/slots 0 1 2 3 + Rs |t5 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 1|0 0 0 1 i i 1|x x x x x| P P |i i i i i i i i i|i i i i i| Rx.L=#u16 - ALU32/slots 0 1 2 3 - TransferImmediate +|0 1 1 1|0 0 1 0 i i 1|x x x x x| P P |i i i i i i i i i|i i i i i| Rx.H=#u16 - ALU32/slots 0 1 2 3 - TransferImmediate +|0 1 1 1|1 0 0 0 i i -|i i i i i| P P |i i i i i i i i i|d d d d d| Rd=#s16 - ALU32/slots 0 1 2 3 - TransferImmediate +|0 1 1 1|0 0 0 0 0 1 1|s s s s s| P P |0 - - - - - - - -|d d d d d| Rd=Rs - ALU32/slots 0 1 2 3 - TransferRegister +|1 1 1 1|0 1 1 0 0 0 0|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=vaddh(Rs,Rt) - ALU32/slots 0 1 2 3 - +|1 1 1 1|0 1 1 0 0 0 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=vaddh(Rs,Rt):sat - ALU32/slots 0 1 2 3 - +|1 1 1 1|0 1 1 0 0 1 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=vadduh(Rs,Rt):sat - ALU32/slots 0 1 2 3 - +|1 1 1 1|0 1 1 1 - 0 0|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=vavgh(Rs,Rt) - ALU32/slots 0 1 2 3 - +|1 1 1 1|0 1 1 1 - 0 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=vavgh(Rs,Rt):sat - ALU32/slots 0 1 2 3 - +|1 1 1 1|0 1 1 1 - 1 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=vnavgh(Rt,Rs) - ALU32/slots 0 1 2 3 - +|1 1 1 1|0 1 1 0 1 0 0|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=vsubh(Rt,Rs) - ALU32/slots 0 1 2 3 - +|1 1 1 1|0 1 1 0 1 0 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=vsubh(Rt,Rs):sat - ALU32/slots 0 1 2 3 - +|1 1 1 1|0 1 1 0 1 1 1|s s s s s| P P |- t t t t t - - -|d d d d d| Rd=vsubuh(Rt,Rs):sat - ALU32/slots 0 1 2 3 - +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 1|0 0 1 1 - 0 0|s s s s s| P P |1 i i i i i i i i|d d d d d| Rdd=combine(Rs,#s8) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|0 0 1 1 - 0 1|s s s s s| P P |1 i i i i i i i i|d d d d d| Rdd=combine(#s8,Rs) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|1 1 0 0 0 l l|l l l l l| P P |l i i i i i i i i|d d d d d| Rdd=combine(#s8,#S8) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|1 1 0 0 1 - -|l l l l l| P P |l i i i i i i i i|d d d d d| Rdd=combine(#s8,#U6) - ALU32 PERM/slots 0 1 2 3 +|1 1 1 1|0 0 1 1 1 0 0|s s s s s| P P |0 t t t t t - - -|d d d d d| Rd=combine(Rt.H,Rs.H) - ALU32 PERM/slots 0 1 2 3 +|1 1 1 1|0 0 1 1 1 0 1|s s s s s| P P |0 t t t t t - - -|d d d d d| Rd=combine(Rt.H,Rs.L) - ALU32 PERM/slots 0 1 2 3 +|1 1 1 1|0 0 1 1 1 1 0|s s s s s| P P |0 t t t t t - - -|d d d d d| Rd=combine(Rt.L,Rs.H) - ALU32 PERM/slots 0 1 2 3 +|1 1 1 1|0 0 1 1 1 1 1|s s s s s| P P |0 t t t t t - - -|d d d d d| Rd=combine(Rt.L,Rs.L) - ALU32 PERM/slots 0 1 2 3 +|1 1 1 1|0 1 0 1 0 - -|s s s s s| P P |0 t t t t t - - -|d d d d d| Rdd=combine(Rs,Rt) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|0 0 1 1 0 u u|s s s s s| P P |0 i i i i i i i i|d d d d d| Rd=mux(Pu,Rs,#s8) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|0 0 1 1 1 u u|s s s s s| P P |0 i i i i i i i i|d d d d d| Rd=mux(Pu,#s8,Rs) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|1 0 1 i i l l|l l l l l| P P |l i i i i i i i i|d d d d d| Rd=mux(Pu,#s8,#S8) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|0 1 0 0 - - -|s s s s s| P P |- t t t t t - u u|d d d d d| Rd=mux(Pu,Rs,Rt) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 0 0 0|s s s s s| P P |0 - - - - - - - -|d d d d d| Rd=aslh(Rs) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 0 0 1|s s s s s| P P |0 - - - - - - - -|d d d d d| Rd=asrh(Rs) - ALU32 PERM/slots 0 1 2 3 +|1 1 1 1|0 1 0 1 1 - -|s s s s s| P P |- t t t t t - - -|d d d d d| Rdd=packhl(Rs,Rt) - ALU32 PERM/slots 0 1 2 3 +|0 1 1 1|0 1 0 0 0 u u|s s s s s| P P |0 i i i i i i i i|d d d d d| if (Pu) Rd=add(Rs,#s8) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 1 0 0 0 u u|s s s s s| P P |1 i i i i i i i i|d d d d d| if (Pu.new) Rd=add(Rs,#s8) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 1 0 0 1 u u|s s s s s| P P |0 i i i i i i i i|d d d d d| if (!Pu) Rd=add(Rs,#s8) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 1 0 0 1 u u|s s s s s| P P |1 i i i i i i i i|d d d d d| if (!Pu.new) Rd=add(Rs,#s8) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 1 1 0 - 0|s s s s s| P P |0 t t t t t 0 u u|d d d d d| if (Pu) Rd=add(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 1 1 0 - 0|s s s s s| P P |0 t t t t t 1 u u|d d d d d| if (!Pu) Rd=add(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 1 1 0 - 0|s s s s s| P P |1 t t t t t 0 u u|d d d d d| if (Pu.new) Rd=add(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 1 1 0 - 0|s s s s s| P P |1 t t t t t 1 u u|d d d d d| if (!Pu.new) Rd=add(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 1|0 0 0 0 0 0 0|s s s s s| P P |1 - 0 0 u u - - -|d d d d d| if (Pu) Rd=aslh(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 0 0 0|s s s s s| P P |1 - 0 1 u u - - -|d d d d d| if (Pu.new) Rd=aslh(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 0 0 0|s s s s s| P P |1 - 1 0 u u - - -|d d d d d| if (!Pu) Rd=aslh(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 0 0 1|s s s s s| P P |1 - 1 1 u u - - -|d d d d d| if (!Pu.new) Rd=aslh(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 0 0 0|s s s s s| P P |1 - 0 0 u u - - -|d d d d d| if (Pu) Rd=asrh(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 0 0 1|s s s s s| P P |1 - 0 1 u u - - -|d d d d d| if (Pu.new) Rd=asrh(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 0 0 1|s s s s s| P P |1 - 1 0 u u - - -|d d d d d| if (!Pu) Rd=asrh(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 0 0 1|s s s s s| P P |1 - 1 1 u u - - -|d d d d d| if (!Pu.new) Rd=asrh(Rs) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 1 0 1 0 0 0|s s s s s| P P |0 t t t t t 0 u u|d d d d d| if (Pu) Rdd=contains(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 1 0 1 0 0 0|s s s s s| P P |0 t t t t t 1 u u|d d d d d| if (!Pu) Rdd=contains(Rs,Rt)- ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 1 0 1 0 0 0|s s s s s| P P |1 t t t t t 0 u u|d d d d d| if (Pu.new) Rdd=contains(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 1 0 1 0 0 0|s s s s s| P P |1 t t t t t 1 u u|d d d d d| if (!Pu.new) Rdd=contains(Rs,Rt)- ALU32 PRED/slots 0 1 2 3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 1 1 1|1 0 0 1 - 0 0|s s s s s| P P |0 t t t t t 0 u u|d d d d d| if (Pu) Rd=and(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 0 0|s s s s s| P P |0 t t t t t 1 u u|d d d d d| if (!Pu) Rd=and(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 0 0|s s s s s| P P |1 t t t t t 0 u u|d d d d d| if (Pu.new) Rd=and(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 0 0|s s s s s| P P |1 t t t t t 1 u u|d d d d d| if (!Pu.new) Rd=and(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 0 1|s s s s s| P P |0 t t t t t 0 u u|d d d d d| if (Pu) Rd=or(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 0 1|s s s s s| P P |0 t t t t t 1 u u|d d d d d| if (!Pu) Rd=or(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 0 1|s s s s s| P P |1 t t t t t 0 u u|d d d d d| if (Pu.new) Rd=or(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 0 1|s s s s s| P P |1 t t t t t 1 u u|d d d d d| if (!Pu.new) Rd=or(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 1 1|s s s s s| P P |0 t t t t t 0 u u|d d d d d| if (Pu) Rd=xor(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 1 1|s s s s s| P P |0 t t t t t 1 u u|d d d d d| if (!Pu) Rd=xor(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 1 1|s s s s s| P P |1 t t t t t 0 u u|d d d d d| if (Pu.new) Rd=xor(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 0 1 - 1 1|s s s s s| P P |1 t t t t t 1 u u|d d d d d| if (!Pu.new) Rd=xor(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 1 1 0 - 1|s s s s s| P P |0 t t t t t 0 u u|d d d d d| if (Pu) Rd=sub(Rt,Rs) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 1 1 0 - 1|s s s s s| P P |0 t t t t t 1 u u|d d d d d| if (!Pu) Rd=sub(Rt,Rs) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 1 1 0 - 1|s s s s s| P P |1 t t t t t 0 u u|d d d d d| if (Pu.new) Rd=sub(Rt,Rs) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|1 0 1 1 0 - 1|s s s s s| P P |1 t t t t t 1 u u|d d d d d| if (!Pu.new) Rd=sub(Rt,Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 0 0|s s s s s| P P |1 - 0 0 u u - - -|d d d d d| if (Pu) Rd=zxtb(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 0 0|s s s s s| P P |1 - 0 1 u u - - -|d d d d d| if (Pu.new) Rd=zxtb(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 0 0|s s s s s| P P |1 - 1 0 u u - - -|d d d d d| if (!Pu) Rd=zxtb(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 0 0|s s s s s| P P |1 - 1 1 u u - - -|d d d d d| if (!Pu.new) Rd=zxtb(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 0 1|s s s s s| P P |1 - 0 0 u u - - -|d d d d d| if (Pu) Rd=sxtb(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 0 1|s s s s s| P P |1 - 0 1 u u - - -|d d d d d| if (Pu.new) Rd=sxtb(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 0 1|s s s s s| P P |1 - 1 0 u u - - -|d d d d d| if (!Pu) Rd=sxtb(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 0 1|s s s s s| P P |1 - 1 1 u u - - -|d d d d d| if (!Pu.new) Rd=sxtb(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 1 0|s s s s s| P P |1 - 0 0 u u - - -|d d d d d| if (Pu) Rd=zxth(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 1 0|s s s s s| P P |1 - 0 1 u u - - -|d d d d d| if (Pu.new) Rd=zxth(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 1 0|s s s s s| P P |1 - 1 0 u u - - -|d d d d d| if (!Pu) Rd=zxth(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 1 0|s s s s s| P P |1 - 1 1 u u - - -|d d d d d| if (!Pu.new) Rd=zxth(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 1 1|s s s s s| P P |1 - 0 0 u u - - -|d d d d d| if (Pu) Rd=sxth(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 1 1|s s s s s| P P |1 - 0 1 u u - - -|d d d d d| if (Pu.new) Rd=sxth(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 1 1|s s s s s| P P |1 - 1 0 u u - - -|d d d d d| if (!Pu) Rd=sxth(Rs) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 0 0 1 1 1|s s s s s| P P |1 - 1 1 u u - - -|d d d d d| if (!Pu.new) Rd=sxth(Rs) - ALU32 PRED/slots 0 1 2 3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 1|1 1 1 0 0 u u|0 i i i i| P P |0 i i i i i i i i|d d d d d| if (Pu) Rd=#s12 - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|1 1 1 0 0 u u|0 i i i i| P P |1 i i i i i i i i|d d d d d| if (Pu.new) Rd=#s12 - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|1 1 1 0 1 u u|0 i i i i| P P |0 i i i i i i i i|d d d d d| if (!Pu) Rd=#s12 - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|1 1 1 0 1 u u|0 i i i i| P P |1 i i i i i i i i|d d d d d| if (!Pu.new) Rd=#s12 - ALU32 PRED/slots 0 1 2 3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 1|0 1 0 1 0 0 i|s s s s s| P P |i i i i i i i i i|0 0 0 d d| Pd=cmp.eq(Rs,#s10) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 1 0 1 0 0 i|s s s s s| P P |i i i i i i i i i|1 0 0 d d| Pd=!cmp.eq(Rs,#s10) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 1 0 1 0 1 i|s s s s s| P P |i i i i i i i i i|0 0 0 d d| Pd=cmp.gt(Rs,#s10) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 1 0 1 0 1 i|s s s s s| P P |i i i i i i i i i|1 0 0 d d| Pd=!cmp.gt(Rs,#s10) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 1 0 1 1 0 0|s s s s s| P P |i i i i i i i i i|0 0 0 d d| Pd=cmp.gtu(Rs,#u9) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 1 0 1 1 0 0|s s s s s| P P |i i i i i i i i i|1 0 0 d d| Pd=!cmp.gtu(Rs,#u9) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 1 1 - 1 0|s s s s s| P P |1 i i i i i i i i|d d d d d| Rd=cmp.eq(Rs,#s8) - ALU32 PRED/slots 0 1 2 3 +|0 1 1 1|0 0 1 1 - 1 1|s s s s s| P P |1 i i i i i i i i|d d d d d| Rd=!cmp.eq(Rs,#s8) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|0 0 1 0 - 0 0|s s s s s| P P |- t t t t t - - -|0 0 0 d d| Pd=cmp.eq(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|0 0 1 0 - 0 0|s s s s s| P P |- t t t t t - - -|1 0 0 d d| Pd=!cmp.eq(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|0 0 1 0 - 1 0|s s s s s| P P |- t t t t t - - -|0 0 0 d d| Pd=cmp.gt(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|0 0 1 0 - 1 0|s s s s s| P P |- t t t t t - - -|1 0 0 d d| Pd=!cmp.gt(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|0 0 1 0 - 1 1|s s s s s| P P |- t t t t t - - -|0 0 0 d d| Pd=cmp.gtu(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|0 0 1 0 - 1 1|s s s s s| P P |- t t t t t - - -|1 0 0 d d| Pd=!cmp.gtu(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|0 0 1 1 0 1 0|s s s s s| P P |- t t t t t - - -|1 0 0 d d| Rd=cmp.eq(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|1 1 1 1|0 0 1 1 0 1 1|s s s s s| P P |- t t t t t - - -|1 0 0 d d| Rd=!cmp.eq(Rs,Rt) - ALU32 PRED/slots 0 1 2 3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 0|1 0 1 1 0 0 0|0 - - s s| P P |1 - - - t t 1 - -|1 - - d d| Pd=fastcorner9(Ps,Pt) - CR/slot 3 +|0 1 1 0|1 0 1 1 0 0 0|1 - - s s| P P |1 - - - t t 1 - -|1 - - d d| Pd=!fastcorner9(Ps,Pt) - CR/slot 3 +|0 1 1 0|1 0 1 1 1 0 0|0 - - s s| P P |0 - - - - - - - -|- - - d d| Pd=any8(Ps) - CR/slot 3 +|0 1 1 0|1 0 1 1 1 0 1|0 - - s s| P P |0 - - - - - - - -|- - - d d| Pd=all8(Ps) - CR/slot 3 +|0 1 1 0|0 0 0 0 0 0 0|s s s s s| P P |- i i i i i - - -|i i - - -| loop0(#r7:2,Rs) - CR/slot 3 +|0 1 1 0|0 0 0 0 0 0 1|s s s s s| P P |- i i i i i - - -|i i - - -| loop1(#r7:2,Rs) - CR/slot 3 +|0 1 1 0|1 0 0 1 0 0 0|l l l l l| P P |- i i i i i l l l|i i - l l| loop1(#r7:2,#U10) - CR/slot 3 +|0 1 1 0|1 0 0 1 0 0 1|l l l l l| P P |- i i i i i l l l|i i - l l| loop1(#r7:2,#U10) - CR/slot 3 +|0 1 1 0|1 0 1 0 0 1 0|0 1 0 0 1| P P |- i i i i i i - -|d d d d d| Rd=add(pc,#u6) - CR/slot 3 +|0 1 1 0|0 0 0 0 1 0 1|s s s s s| P P |- i i i i i - - -|i i - - -| p3=sp1loop0(#r7:2,Rs) - CR/slot 3 +|0 1 1 0|0 0 0 0 1 1 0|s s s s s| P P |- i i i i i - - -|i i - - -| p3=sp2loop0(#r7:2,Rs) - CR/slot 3 +|0 1 1 0|0 0 0 0 1 1 1|s s s s s| P P |- i i i i i - - -|i i - - -| p3=sp3loop0(#r7:2,Rs) - CR/slot 3 +|0 1 1 0|1 0 0 1 1 0 1|l l l l l| P P |- i i i i i l l l|i i - l l| p3=sp1loop0(#r7:2,#U10) - CR/slot 3 +|0 1 1 0|1 0 0 1 1 1 0|l l l l l| P P |- i i i i i l l l|i i - l l| p3=sp2loop0(#r7:2,#U10) - CR/slot 3 +|0 1 1 0|1 0 0 1 1 1 1|l l l l l| P P |- i i i i i l l l|i i - l l| p3=sp3loop0(#r7:2,#U10) - CR/slot 3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 0|1 0 1 1 0 0 0|0 - - s s| P P |0 - - - t t - - -|- - - d d| Pd=and(Pt,Ps) - CR/slot 3 +|0 1 1 0|1 0 1 1 0 0 0|1 - - s s| P P |0 - - - t t u u -|- - - d d| Pd=and(Ps,and(Pt,Pu)) - CR/slot 3 +|0 1 1 0|1 0 1 1 0 0 1|0 - - s s| P P |0 - - - t t - - -|- - - d d| Pd=or(Pt,Ps) - CR/slot 3 +|0 1 1 0|1 0 1 1 0 0 1|1 - - s s| P P |0 - - - t t u u -|- - - d d| Pd=or(Ps,or(Pt,Pu)) - CR/slot 3 +|0 1 1 0|1 0 1 1 0 1 0|0 - - s s| P P |0 - - - t t - - -|- - - d d| Pd=xor(Pt,Ps) - CR/slot 3 +|0 1 1 0|1 0 1 1 0 1 0|1 - - s s| P P |0 - - - t t u u -|- - - d d| Pd=or(Ps,and(Pt,Pu)) - CR/slot 3 +|0 1 1 0|1 0 1 1 0 1 1|0 - - s s| P P |0 - - - t t - - -|- - - d d| Pd=and(Pt,!Ps) - CR/slot 3 +|0 1 1 0|1 0 1 1 0 1 1|1 - - s s| P P |0 - - - t t u u -|- - - d d| Pd=or(Ps,or(Pt,Pu)) - CR/slot 3 +|0 1 1 0|1 0 1 1 1 0 0|1 - - s s| P P |0 - - - t t u u -|- - - d d| Pd=and(Ps,and(Pt,Pu)) - CR/slot 3 +|0 1 1 0|1 0 1 1 1 0 1|1 - - s s| P P |0 - - - t t u u -|- - - d d| Pd=and(Ps,or(Pt,Pu)) - CR/slot 3 +|0 1 1 0|1 0 1 1 1 1 0|0 - - s s| P P |0 - - - - - - - -|- - - d d| Pd=not(Ps) - CR/slot 3 +|0 1 1 0|1 0 1 1 1 1 0|1 - - s s| P P |0 - - - t t u u -|- - - d d| Pd=or(Ps,and(Pt,Pu)) - CR/slot 3 +|0 1 1 0|1 0 1 1 1 1 1|0 - - s s| P P |0 - - - t t - - -|- - - d d| Pd=or(Pt,!Ps) - CR/slot 3 +|0 1 1 0|1 0 1 1 1 1 1|1 - - s s| P P |0 - - - t t u u -|- - - d d| Pd=or(Ps,or(Pt,Pu)) - CR/slot 3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 0|0 0 1 0 0 0 1|s s s s s| P P |- - - - - - - - -|d d d d d| Cd=Rs - CR/slot 3 - CONTROL REGISTERS ARE NOT NUMBERED NORMALLY +|0 1 1 0|0 0 1 1 0 0 1|s s s s s| P P |- - - - - - - - -|d d d d d| Cdd=Rss - CR/slot 3 - CONTROL REGISTERS ARE NOT NUMBERED NORMALLY +|0 1 1 0|1 0 0 0 0 0 0|s s s s s| P P |- - - - - - - - -|d d d d d| Rss=Cdd - CR/slot 3 - CONTROL REGISTERS ARE NOT NUMBERED NORMALLY +|0 1 1 0|1 0 1 0 0 0 0|s s s s s| P P |- - - - - - - - -|d d d d d| Rs=Cd - CR/slot 3 - CONTROL REGISTERS ARE NOT NUMBERED NORMALLY + +|0 1 0 1|0 0 0 0 1 0 1|s s s s s| P P |- - - - - - - - -|- - - - -| callr Rs - CR/slot 2 +|0 1 0 1|0 0 0 0 1 1 0|s s s s s| P P |- - - - - - - - -|- - - - -| callrh Rs - CR/slot 2 +|0 1 0 1|0 0 0 1 0 0 0|s s s s s| P P |- - - - u u - - -|- - - - -| if (Pu) callr Rs - CR/slot 2 +|0 1 0 1|0 0 0 1 0 0 1|s s s s s| P P |- - - - u u - - -|- - - - -| if (!Pu) callr Rs - CR/slot 2 +|0 1 0 1|0 0 1 0 1 0 0|s s s s s| P P |- - - - - - - - -|- - - - -| jumpr Rs - CR/slot 2 +|0 1 0 1|0 0 1 0 1 1 0|s s s s s| P P |- - - - - - - - -|- - - - -| jumprh Rs - CR/slot 2 +|0 1 0 1|0 0 1 0 1 0 1|s s s s s| P P |- - - - - - - - -|- - - - -| hintjr(Rs) - CR/slot 2,3 +|0 1 0 1|0 0 1 1 0 1 0|s s s s s| P P |- 0 0 - u u - - -|- - - - -| if (Pu) jumpr:nt Rs - CR/slot 2 +|0 1 0 1|0 0 1 1 0 1 0|s s s s s| P P |- 0 1 - u u - - -|- - - - -| if (Pu.new) jumpr:nt Rs - CR/slot 2 +|0 1 0 1|0 0 1 1 0 1 0|s s s s s| P P |- 1 0 - u u - - -|- - - - -| if (Pu) jumpr:t Rs - CR/slot 2 +|0 1 0 1|0 0 1 1 0 1 0|s s s s s| P P |- 1 1 - u u - - -|- - - - -| if (Pu.new) jumpr:t Rs - CR/slot 2 +|0 1 0 1|0 0 1 1 0 1 1|s s s s s| P P |- 0 0 - u u - - -|- - - - -| if (!Pu) jumpr:nt Rs - CR/slot 2 +|0 1 0 1|0 0 1 1 0 1 1|s s s s s| P P |- 0 1 - u u - - -|- - - - -| if (!Pu.new) jumpr:nt Rs - CR/slot 2 +|0 1 0 1|0 0 1 1 0 1 1|s s s s s| P P |- 1 0 - u u - - -|- - - - -| if (!Pu) jumpr:t Rs - CR/slot 2 +|0 1 0 1|0 0 1 1 0 1 1|s s s s s| P P |- 1 1 - u u - - -|- - - - -| if (!Pu.new) jumpr:t Rs - CR/slot 2 +|0 1 0 1|1 0 1 i i i i|i i i i i| P P |i i i i i i i i i|i i i i 0| call #r22:2 - CR/slot 2,3 +|0 1 0 1|1 1 0 1 i i 0|i i i i i| P P |i - 0 - u u i i i|i i i i -| if (Pu) call #r15:2 - CR/slot 2,3 +|0 1 0 1|1 1 0 1 i i 1|i i i i i| P P |i - 0 - u u i i i|i i i i -| if (!Pu) call #r15:2 - CR/slot 2,3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 0 1|0 0 0 1 1 0 i|i s s s s| P P |0 - - - 0 0 i i i|i i i i -| p0=cmp.eq(Rs,#-1); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 0 i|i s s s s| P P |0 - - - 0 1 i i i|i i i i -| p0=cmp.gt(Rs,#-1); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 0 i|i s s s s| P P |0 - - - 1 1 i i i|i i i i -| p0=tstbit(Rs,#0); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 0 i|i s s s s| P P |1 - - - 0 0 i i i|i i i i -| p0=cmp.eq(Rs,#-1); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 0 i|i s s s s| P P |1 - - - 0 1 i i i|i i i i -| p0=cmp.gt(Rs,#-1); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 0 i|i s s s s| P P |1 - - - 1 1 i i i|i i i i -| p0=tstbit(Rs,#0); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 1 i|i s s s s| P P |0 - - - 0 0 i i i|i i i i -| p0=cmp.eq(Rs,#-1); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 1 i|i s s s s| P P |0 - - - 0 1 i i i|i i i i -| p0=cmp.gt(Rs,#-1); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 1 i|i s s s s| P P |0 - - - 1 1 i i i|i i i i -| p0=tstbit(Rs,#0); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 1 i|i s s s s| P P |1 - - - 0 0 i i i|i i i i -| p0=cmp.eq(Rs,#-1); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 1 i|i s s s s| P P |1 - - - 0 1 i i i|i i i i -| p0=cmp.gt(Rs,#-1); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 1 1 i|i s s s s| P P |1 - - - 1 1 i i i|i i i i -| p0=tstbit(Rs,#0); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 + +|0 0 0 1|0 0 0 0 0 0 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p0=cmp.eq(Rs,#U5); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 0 0 0 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p0=cmp.eq(Rs,#U5); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 0 0 1 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p0=cmp.eq(Rs,#U5); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 0 0 1 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p0=cmp.eq(Rs,#U5); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 0 1 0 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p0=cmp.gt(Rs,#U5); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 0 1 0 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p0=cmp.gt(Rs,#U5); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 0 1 1 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p0=cmp.gt(Rs,#U5); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 0 1 1 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p0=cmp.gt(Rs,#U5); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 0 0 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p0=cmp.gtu(Rs,#U5); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 0 0 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p0=cmp.gtu(Rs,#U5); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 0 1 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 0 1 0 1 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 + +|0 0 0 1|0 0 1 0 0 0 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p1=cmp.eq(Rs,#U5); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 0 0 0 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p1=cmp.eq(Rs,#U5); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 0 0 1 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p1=cmp.eq(Rs,#U5); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 0 0 1 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p1=cmp.eq(Rs,#U5); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 0 1 0 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p1=cmp.gt(Rs,#U5); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 0 1 0 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p1=cmp.gt(Rs,#U5); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 0 1 1 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p1=cmp.gt(Rs,#U5); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 0 1 1 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p1=cmp.gt(Rs,#U5); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 0 0 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p1=cmp.gtu(Rs,#U5); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 0 0 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p1=cmp.gtu(Rs,#U5); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 0 1 i|i s s s s| P P |0 l l l l l i i i|i i i i -| p1=cmp.gtu(Rs,#U5); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 0 1 i|i s s s s| P P |1 l l l l l i i i|i i i i -| p1=cmp.gtu(Rs,#U5); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 + +|0 0 0 1|0 0 1 1 1 0 i|i s s s s| P P |0 - - - 0 0 i i i|i i i i -| p1=cmp.eq(Rs,#-1); if (p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 0 i|i s s s s| P P |0 - - - 0 1 i i i|i i i i -| p1=cmp.gt(Rs,#-1); if (p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 0 i|i s s s s| P P |0 - - - 1 1 i i i|i i i i -| p1=tstbit(Rs,#0); if (p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 0 i|i s s s s| P P |1 - - - 0 0 i i i|i i i i -| p1=cmp.eq(Rs,#-1); if (p1.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 0 i|i s s s s| P P |1 - - - 0 1 i i i|i i i i -| p1=cmp.gt(Rs,#-1); if (p1.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 0 i|i s s s s| P P |1 - - - 1 1 i i i|i i i i -| p1=tstbit(Rs,#0); if (p1.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 1 i|i s s s s| P P |0 - - - 0 0 i i i|i i i i -| p1=cmp.eq(Rs,#-1); if (!p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 1 i|i s s s s| P P |0 - - - 0 1 i i i|i i i i -| p1=cmp.gt(Rs,#-1); if (!p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 1 i|i s s s s| P P |0 - - - 1 1 i i i|i i i i -| p1=tstbit(Rs,#0); if (!p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 1 i|i s s s s| P P |1 - - - 0 0 i i i|i i i i -| p1=cmp.eq(Rs,#-1); if (!p1.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 1 i|i s s s s| P P |1 - - - 0 1 i i i|i i i i -| p1=cmp.gt(Rs,#-1); if (!p1.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 0 1 1 1 1 i|i s s s s| P P |1 - - - 1 1 i i i|i i i i -| p1=tstbit(Rs,#0); if (!p1.new) jump:t #r9:2 - J/slot 0,1,2,3 + +|0 0 0 1|0 1 0 0 0 0 i|i s s s s| P P |0 0 t t t t i i i|i i i i -| p0=cmp.eq(Rs,Rt); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 0 0 i|i s s s s| P P |0 1 t t t t i i i|i i i i -| p1=cmp.eq(Rs,Rt); if (p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 0 0 i|i s s s s| P P |1 0 t t t t i i i|i i i i -| p0=cmp.eq(Rs,Rt); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 0 0 i|i s s s s| P P |1 1 t t t t i i i|i i i i -| p1=cmp.eq(Rs,Rt); if (p1.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 0 1 i|i s s s s| P P |0 0 t t t t i i i|i i i i -| p0=cmp.eq(Rs,Rt); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 0 1 i|i s s s s| P P |0 1 t t t t i i i|i i i i -| p1=cmp.eq(Rs,Rt); if (!p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 0 1 i|i s s s s| P P |1 0 t t t t i i i|i i i i -| p0=cmp.eq(Rs,Rt); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 0 1 i|i s s s s| P P |1 1 t t t t i i i|i i i i -| p1=cmp.eq(Rs,Rt); if (!p1.new) jump:t #r9:2 - J/slot 0,1,2,3 + +|0 0 0 1|0 1 0 0 1 0 i|i s s s s| P P |0 0 t t t t i i i|i i i i -| p0=cmp.gt(Rs,Rt); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 1 0 i|i s s s s| P P |0 1 t t t t i i i|i i i i -| p1=cmp.gt(Rs,Rt); if (p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 1 0 i|i s s s s| P P |1 0 t t t t i i i|i i i i -| p0=cmp.gt(Rs,Rt); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 1 0 i|i s s s s| P P |1 1 t t t t i i i|i i i i -| p1=cmp.gt(Rs,Rt); if (p1.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 1 1 i|i s s s s| P P |0 0 t t t t i i i|i i i i -| p0=cmp.gt(Rs,Rt); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 1 1 i|i s s s s| P P |0 1 t t t t i i i|i i i i -| p1=cmp.gt(Rs,Rt); if (!p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 1 1 i|i s s s s| P P |1 0 t t t t i i i|i i i i -| p0=cmp.gt(Rs,Rt); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 0 1 1 i|i s s s s| P P |1 1 t t t t i i i|i i i i -| p1=cmp.gt(Rs,Rt); if (!p1.new) jump:t #r9:2 - J/slot 0,1,2,3 + +|0 0 0 1|0 1 0 1 0 0 i|i s s s s| P P |0 0 t t t t i i i|i i i i -| p0=cmp.gtu(Rs,Rt); if (p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 1 0 0 i|i s s s s| P P |0 1 t t t t i i i|i i i i -| p1=cmp.gtu(Rs,Rt); if (p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 1 0 0 i|i s s s s| P P |1 0 t t t t i i i|i i i i -| p0=cmp.gtu(Rs,Rt); if (p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 1 0 0 i|i s s s s| P P |1 1 t t t t i i i|i i i i -| p1=cmp.gtu(Rs,Rt); if (p1.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 1 0 1 i|i s s s s| P P |0 0 t t t t i i i|i i i i -| p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 1 0 1 i|i s s s s| P P |0 1 t t t t i i i|i i i i -| p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:nt #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 1 0 1 i|i s s s s| P P |1 0 t t t t i i i|i i i i -| p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:t #r9:2 - J/slot 0,1,2,3 +|0 0 0 1|0 1 0 1 0 1 i|i s s s s| P P |1 1 t t t t i i i|i i i i -| p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:t #r9:2 - J/slot 0,1,2,3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 0 1|1 0 0 i i i i|i i i i i| P P |i i i i i i i i i|i i i i -| jump #r22:2 - J/slot 0,1,2,3 +|0 1 0 1|1 1 0 0 i i 0|i i i i i| P P |i 0 0 - u u i i i|i i i i -| if (Pu) jump:nt #r15:2 - J/slot 0,1,2,3 +|0 1 0 1|1 1 0 0 i i 0|i i i i i| P P |i 1 0 - u u i i i|i i i i -| if (Pu) jump:t #r15:2 - J/slot 0,1,2,3 +|0 1 0 1|1 1 0 0 i i 1|i i i i i| P P |i 0 0 - u u i i i|i i i i -| if (!Pu) jump:nt #r15:2 - J/slot 0,1,2,3 +|0 1 0 1|1 1 0 0 i i 1|i i i i i| P P |i 1 0 - u u i i i|i i i i -| if (!Pu) jump:t #r15:2 - J/slot 0,1,2,3 +|0 1 0 1|1 1 0 0 i i 0|i i i i i| P P |i 0 1 - u u i i i|i i i i -| if (Pu.new) jump:nt #r15:2 - J/slot 0,1,2,3 +|0 1 0 1|1 1 0 0 i i 0|i i i i i| P P |i 1 1 - u u i i i|i i i i -| if (Pu.new) jump:t #r15:2 - J/slot 0,1,2,3 +|0 1 0 1|1 1 0 0 i i 1|i i i i i| P P |i 0 1 - u u i i i|i i i i -| if (!Pu.new) jump:nt #r15:2 - J/slot 0,1,2,3 +|0 1 0 1|1 1 0 0 i i 1|i i i i i| P P |i 1 1 - u u i i i|i i i i -| if (!Pu.new) jump:t #r15:2 - J/slot 0,1,2,3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 0|0 0 0 1 0 0 i|s s s s s| P P |i 0 i i i i i i i|i i i i -| if (Rs!=#0) jump:nt #r13:2 - J/slot 3 +|0 1 1 0|0 0 0 1 0 0 i|s s s s s| P P |i 1 i i i i i i i|i i i i -| if (Rs!=#0) jump:t #r13:2 - J/slot 3 +|0 1 1 0|0 0 0 1 0 1 i|s s s s s| P P |i 0 i i i i i i i|i i i i -| if (Rs>=#0) jump:nt #r13:2 - J/slot 3 +|0 1 1 0|0 0 0 1 0 1 i|s s s s s| P P |i 1 i i i i i i i|i i i i -| if (Rs>=#0) jump:t #r13:2 - J/slot 3 +|0 1 1 0|0 0 0 1 0 1 i|s s s s s| P P |i 0 i i i i i i i|i i i i -| if (Rs==#0) jump:nt #r13:2 - J/slot 3 +|0 1 1 0|0 0 0 1 0 1 i|s s s s s| P P |i 1 i i i i i i i|i i i i -| if (Rs==#0) jump:t #r13:2 - J/slot 3 +|0 1 1 0|0 0 0 1 1 1 i|s s s s s| P P |i 0 i i i i i i i|i i i i -| if (Rs<=#0) jump:nt #r13:2 - J/slot 3 +|0 1 1 0|0 0 0 1 1 1 i|s s s s s| P P |i 1 i i i i i i i|i i i i -| if (Rs<=#0) jump:t #r13:2 - J/slot 3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 0 1|0 1 1 0 - - i|i d d d d| P P |l l l l l l i i i|i i i i -| Rd=#U6; jump #r9:2 - J/slot 2,3 +|0 0 0 1|0 1 1 1 - - i|i s s s s| P P |- - d d d d i i i|i i i i -| Rd=Rs; jump #r9:2 - J/slot 2,3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 0 1 1 0|s s s s s| P P |i t t t t t i - -|d d d d d| Rdd=memd(Rs+Rt<<#u2) - LD/slot 0,1 +|0 1 0 0|1 i i 1 1 1 0|i i i i i| P P |i i i i i i i i i|d d d d d| Rdd=memd(gp+#u16:3) - LD/slot 0,1 +|1 0 0 1|0 i i 1 1 1 0|s s s s s| P P |i i i i i i i i i|d d d d d| Rdd=memd(Rs+#s11:3) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 1 1 0|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rdd=memd(Rx++#s4:3:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 1 1 0|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rdd=memd(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 1 0|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rdd=memd(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 1 0|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rdd=memd(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 1 1 0|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rdd=memd(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 1 1 0|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=memd(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 1 1 0|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=memd(Rx++Mu:brev) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 0 1 0 0 0 0|s s s s s| P P |0 1 1 - - - 0 0 0|d d d d d| Rdd=memd_aq(Rs) - LD/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 0 0 0 1 1 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv) Rdd=memd(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 0 1 1 1 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv) Rdd=memd(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 0 1 1 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv.new) Rdd=memd(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 1 1 1 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv.new) Rdd=memd(Rs+Rt<<#u2) - LD/slot 0,1 + +|0 1 0 0|0 0 1 1 1 1 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt) Rdd=memd(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 0 0 1 1 1 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt) Rdd=memd(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 1 1 1 1 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt.new) Rdd=memd(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 0 1 1 1 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt.new) Rdd=memd(Rs+#u6:3) - LD/slot 0,1 + +|1 0 0 1|1 0 1 1 1 1 0|x x x x x| P P |1 0 0 t t i i i i|d d d d d| if (Pt) Rdd=memd(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 1 0|x x x x x| P P |1 0 1 t t i i i i|d d d d d| if (!Pt) Rdd=memd(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 1 0|x x x x x| P P |1 1 0 t t i i i i|d d d d d| if (Pt.new) Rdd=memd(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 1 0|x x x x x| P P |1 1 1 t t i i i i|d d d d d| if (!Pt.new) Rdd=memd(Rx++#s4:3) - LD/slot 0,1 + +|1 0 0 1|1 1 1 1 1 1 0|i i i i i| P P |1 0 0 t t i 1 - -|d d d d d| if (Pt) Rdd=memd(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 1 1 0|i i i i i| P P |1 0 1 t t i 1 - -|d d d d d| if (!Pt) Rdd=memd(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 1 1 0|i i i i i| P P |1 1 0 t t i 1 - -|d d d d d| if (Pt.new) Rdd=memd(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 1 1 0|i i i i i| P P |1 1 1 t t i 1 - -|d d d d d| if (!Pt.new) Rdd=memd(#u6) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 0 0 0 0|s s s s s| P P |i t t t t t i - -|d d d d d| Rd=memb(Rs+Rt<<#u2) - LD/slot 0,1 +|0 1 0 0|1 i i 1 0 0 0|i i i i i| P P |i i i i i i i i i|d d d d d| Rd=memb(gp+#u16:3) - LD/slot 0,1 +|1 0 0 1|0 i i 1 0 0 0|s s s s s| P P |i i i i i i i i i|d d d d d| Rd=memb(Rs+#s11:3) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 0 0 0|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rd=memb(Rx++#s4:3:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 0 0 0|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rd=memb(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 0|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rd=memb(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 0|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rd=memb(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 0 0 0|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rd=memb(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 0 0 0|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=memb(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 0 0|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=memb(Rx++Mu:brev) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 0 0 0 0 0 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv) Rd=memb(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 0 1 0 0 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv) Rd=memb(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 0 0 0 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv.new) Rd=memb(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 1 0 0 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv.new) Rd=memb(Rs+Rt<<#u2) - LD/slot 0,1 + +|0 1 0 0|0 0 1 1 0 0 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt) Rd=memb(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 0 0 1 0 0 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt) Rd=memb(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 1 1 0 0 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt.new) Rd=memb(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 0 1 0 0 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt.new) Rd=memb(Rs+#u6:3) - LD/slot 0,1 + +|1 0 0 1|1 0 1 1 0 0 0|x x x x x| P P |1 0 0 t t i i i i|d d d d d| if (Pt) Rd=memb(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 0|x x x x x| P P |1 0 1 t t i i i i|d d d d d| if (!Pt) Rd=memb(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 0|x x x x x| P P |1 1 0 t t i i i i|d d d d d| if (Pt.new) Rd=memb(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 0|x x x x x| P P |1 1 1 t t i i i i|d d d d d| if (!Pt.new) Rd=memb(Rx++#s4:3) - LD/slot 0,1 + +|1 0 0 1|1 1 1 1 0 0 0|i i i i i| P P |1 0 0 t t i 1 - -|d d d d d| if (Pt) Rd=memb(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 0 0|i i i i i| P P |1 0 1 t t i 1 - -|d d d d d| if (!Pt) Rd=memb(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 0 0|i i i i i| P P |1 1 0 t t i 1 - -|d d d d d| if (Pt.new) Rd=memb(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 0 0|i i i i i| P P |1 1 1 t t i 1 - -|d d d d d| if (!Pt.new) Rd=memb(#u6) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 i i 0 1 0 0|s s s s s| P P |i i i i i i i i i|y y y y y| Ryy=memb_fifo(Rs+#s11:0) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 1 0 0|x x x x x| P P |u 0 - - 0 i i i i|y y y y y| Ryy=memb_fifo(Rx++#s4:0:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 1 0 0|x x x x x| P P |u 0 - - 1 - 0 - -|y y y y y| Ryy=memb_fifo(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 1 0 0|e e e e e| P P |0 1 l l l l - l l|y y y y y| Ryy=memb_fifo(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 1 0 0|x x x x x| P P |0 0 - - - i i i i|y y y y y| Ryy=memb_fifo(Rx++#s4:0) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 1 0 0|t t t t t| P P |i 1 l l l l i l l|y y y y y| Ryy=memb_fifo(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 1 0 0|x x x x x| P P |u 0 - - - - 0 - -|y y y y y| Ryy=memb_fifo(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 1 0 1 0 0|x x x x x| P P |u 0 - - - - 0 - -|y y y y y| Ryy=memb_fifo(Rx++Mu:brev) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 i i 0 0 1 0|s s s s s| P P |i i i i i i i i i|y y y y y| Ryy=memh_fifo(Rs+#s11:0) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 0 1 0|x x x x x| P P |u 0 - - 0 i i i i|y y y y y| Ryy=memh_fifo(Rx++#s4:0:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 0 1 0|x x x x x| P P |u 0 - - 1 - 0 - -|y y y y y| Ryy=memh_fifo(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 0 1 0|e e e e e| P P |0 1 l l l l - l l|y y y y y| Ryy=memh_fifo(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 0 1 0|x x x x x| P P |0 0 - - - i i i i|y y y y y| Ryy=memh_fifo(Rx++#s4:0) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 0 1 0|t t t t t| P P |i 1 l l l l i l l|y y y y y| Ryy=memh_fifo(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 0 1 0|x x x x x| P P |u 0 - - - - 0 - -|y y y y y| Ryy=memh_fifo(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 1 0 0 1 0|x x x x x| P P |u 0 - - - - 0 - -|y y y y y| Ryy=memh_fifo(Rx++Mu:brev) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 0 0 1 0|s s s s s| P P |i t t t t t i - -|d d d d d| Rd=memh(Rs+Rt<<#u2) - LD/slot 0,1 +|0 1 0 0|1 i i 1 0 1 0|i i i i i| P P |i i i i i i i i i|d d d d d| Rd=memh(gp+#u16:3) - LD/slot 0,1 +|1 0 0 1|0 i i 1 0 1 0|s s s s s| P P |i i i i i i i i i|d d d d d| Rd=memh(Rs+#s11:3) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 0 1 0|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rd=memh(Rx++#s4:3:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 0 1 0|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rd=memh(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 0|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rd=memh(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 0|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rd=memh(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 0 1 0|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rd=memh(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 0 1 0|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=memh(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 1 0|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=memh(Rx++Mu:brev) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 0 0 0 0 1 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv) Rd=memh(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 0 1 0 1 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv) Rd=memh(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 0 0 1 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv.new) Rd=memh(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 1 0 1 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv.new) Rd=memh(Rs+Rt<<#u2) - LD/slot 0,1 + +|0 1 0 0|0 0 1 1 0 1 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt) Rd=memh(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 0 0 1 0 1 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt) Rd=memh(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 1 1 0 1 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt.new) Rd=memh(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 0 1 0 1 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt.new) Rd=memh(Rs+#u6:3) - LD/slot 0,1 + +|1 0 0 1|1 0 1 1 0 1 0|x x x x x| P P |1 0 0 t t i i i i|d d d d d| if (Pt) Rd=memh(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 0|x x x x x| P P |1 0 1 t t i i i i|d d d d d| if (!Pt) Rd=memh(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 0|x x x x x| P P |1 1 0 t t i i i i|d d d d d| if (Pt.new) Rd=memh(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 0|x x x x x| P P |1 1 1 t t i i i i|d d d d d| if (!Pt.new) Rd=memh(Rx++#s4:3) - LD/slot 0,1 + +|1 0 0 1|1 1 1 1 0 1 0|i i i i i| P P |1 0 0 t t i 1 - -|d d d d d| if (Pt) Rd=memh(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 1 0|i i i i i| P P |1 0 1 t t i 1 - -|d d d d d| if (!Pt) Rd=memh(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 1 0|i i i i i| P P |1 1 0 t t i 1 - -|d d d d d| if (Pt.new) Rd=memh(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 1 0|i i i i i| P P |1 1 1 t t i 1 - -|d d d d d| if (!Pt.new) Rd=memh(#u6) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|1 0 0 1 1 1 1|t t t t t| P P |0 x x x x x 0 0 0|d d d d d| Rdd=pmemcpy(Rx,Rtt) - LD/slot 0,1 - Solo +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 0|1 1 1 1 1 1 1|t t t t t| P P |0 s s s s s 0 1 0|d d d d d| Rd=movlen(Rs,Rtt) - LD/slot 0,1 - Solo +|1 0 0 1|1 0 0 1 1 1 1|t t t t t| P P |0 s s s s s 0 0 1|d d d d d| Rdd=linecpy(Rs,Rtt) - LD/slot 0,1 - Solo +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 0 0 0 1|s s s s s| P P |i t t t t t i - -|d d d d d| Rdd=memub(Rs+Rt<<#u2) - LD/slot 0,1 +|0 1 0 0|1 i i 1 0 0 1|i i i i i| P P |i i i i i i i i i|d d d d d| Rdd=memub(gp+#u16:3) - LD/slot 0,1 +|1 0 0 1|0 i i 1 0 0 1|s s s s s| P P |i i i i i i i i i|d d d d d| Rdd=memub(Rs+#s11:3) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 0 0 1|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rdd=memub(Rx++#s4:3:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 0 0 1|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rdd=memub(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 1|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rdd=memub(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 1|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rdd=memub(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 0 0 1|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rdd=memub(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 0 0 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=memub(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 0 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=memub(Rx++Mu:brev) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 0 0 0 0 0 1|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv) Rd=memub(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 0 1 0 0 1|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv) Rd=memub(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 0 0 0 1|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv.new) Rd=memub(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 1 0 0 1|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv.new) Rd=memub(Rs+Rt<<#u2) - LD/slot 0,1 + +|0 1 0 0|0 0 1 1 0 0 1|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt) Rd=memub(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 0 0 1 0 0 1|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt) Rd=memub(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 1 1 0 0 1|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt.new) Rd=memub(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 0 1 0 0 1|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt.new) Rd=memub(Rs+#u6:3) - LD/slot 0,1 + +|1 0 0 1|1 0 1 1 0 0 1|x x x x x| P P |1 0 0 t t i i i i|d d d d d| if (Pt) Rd=memub(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 1|x x x x x| P P |1 0 1 t t i i i i|d d d d d| if (!Pt) Rd=memub(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 1|x x x x x| P P |1 1 0 t t i i i i|d d d d d| if (Pt.new) Rd=memub(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 0 1|x x x x x| P P |1 1 1 t t i i i i|d d d d d| if (!Pt.new) Rd=memub(Rx++#s4:3) - LD/slot 0,1 + +|1 0 0 1|1 1 1 1 0 0 1|i i i i i| P P |1 0 0 t t i 1 - -|d d d d d| if (Pt) Rd=memub(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 0 1|i i i i i| P P |1 0 1 t t i 1 - -|d d d d d| if (!Pt) Rd=memub(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 0 1|i i i i i| P P |1 1 0 t t i 1 - -|d d d d d| if (Pt.new) Rd=memub(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 0 1|i i i i i| P P |1 1 1 t t i 1 - -|d d d d d| if (!Pt.new) Rd=memub(#u6) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 0 0 1 1|s s s s s| P P |i t t t t t i - -|d d d d d| Rdd=memuh(Rs+Rt<<#u2) - LD/slot 0,1 +|0 1 0 0|1 i i 1 0 1 1|i i i i i| P P |i i i i i i i i i|d d d d d| Rdd=memuh(gp+#u16:3) - LD/slot 0,1 +|1 0 0 1|0 i i 1 0 1 1|s s s s s| P P |i i i i i i i i i|d d d d d| Rdd=memuh(Rs+#s11:3) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 0 1 1|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rdd=memuh(Rx++#s4:3:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 0 1 1|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rdd=memuh(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 1|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rdd=memuh(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 1|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rdd=memuh(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 0 1 1|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rdd=memuh(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 0 1 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=memuh(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 1 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=memuh(Rx++Mu:brev) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 0 0 0 0 1 1|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv) Rd=memuh(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 0 1 0 1 1|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv) Rd=memuh(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 0 0 1 1|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv.new) Rd=memuh(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 1 0 1 1|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv.new) Rd=memuh(Rs+Rt<<#u2) - LD/slot 0,1 + +|0 1 0 0|0 0 1 1 0 1 1|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt) Rd=memuh(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 0 0 1 0 1 1|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt) Rd=memuh(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 1 1 0 1 1|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt.new) Rd=memuh(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 0 1 0 1 1|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt.new) Rd=memuh(Rs+#u6:3) - LD/slot 0,1 + +|1 0 0 1|1 0 1 1 0 1 1|x x x x x| P P |1 0 0 t t i i i i|d d d d d| if (Pt) Rd=memuh(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 1|x x x x x| P P |1 0 1 t t i i i i|d d d d d| if (!Pt) Rd=memuh(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 1|x x x x x| P P |1 1 0 t t i i i i|d d d d d| if (Pt.new) Rd=memuh(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 0 1 1|x x x x x| P P |1 1 1 t t i i i i|d d d d d| if (!Pt.new) Rd=memuh(Rx++#s4:3) - LD/slot 0,1 + +|1 0 0 1|1 1 1 1 0 1 1|i i i i i| P P |1 0 0 t t i 1 - -|d d d d d| if (Pt) Rd=memuh(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 1 1|i i i i i| P P |1 0 1 t t i 1 - -|d d d d d| if (!Pt) Rd=memuh(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 1 1|i i i i i| P P |1 1 0 t t i 1 - -|d d d d d| if (Pt.new) Rd=memuh(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 0 1 1|i i i i i| P P |1 1 1 t t i 1 - -|d d d d d| if (!Pt.new) Rd=memuh(#u6) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 0 1 0 0|s s s s s| P P |i t t t t t i - -|d d d d d| Rd=memw(Rs+Rt<<#u2) - LD/slot 0,1 +|0 1 0 0|1 i i 1 1 0 0|i i i i i| P P |i i i i i i i i i|d d d d d| Rd=memw(gp+#u16:3) - LD/slot 0,1 +|1 0 0 1|0 i i 1 1 0 0|s s s s s| P P |i i i i i i i i i|d d d d d| Rd=memw(Rs+#s11:3) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 1 0 0|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rd=memw(Rx++#s4:3:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 1 1 0 0|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rd=memw(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 0 0|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rd=memw(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 0 0|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rd=memw(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 1 0 0|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rd=memw(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 1 1 0 0|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=memw(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 1 0 0|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=memw(Rx++Mu:brev) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 0 1 0 0 0 0|s s s s s| P P |0 0 1 - - - 0 0 0|d d d d d| Rd=memw_aq(Rs) - LD/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 0 0 0 1 0 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv) Rd=memw(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 0 1 1 0 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv) Rd=memw(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 0 1 0 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (Pv.new) Rd=memw(Rs+Rt<<#u2) - LD/slot 0,1 +|0 0 1 1|0 0 1 1 1 0 0|s s s s s| P P |i t t t t t i v v|d d d d d| if (!Pv.new) Rd=memw(Rs+Rt<<#u2) - LD/slot 0,1 + +|0 1 0 0|0 0 1 1 1 0 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt) Rd=memw(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 0 0 1 1 0 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt) Rd=memw(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 1 1 1 0 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (Pt.new) Rd=memw(Rs+#u6:3) - LD/slot 0,1 +|0 1 0 0|0 1 0 1 1 0 0|s s s s s| P P |0 t t i i i i i i|d d d d d| if (!Pt.new) Rd=memw(Rs+#u6:3) - LD/slot 0,1 + +|1 0 0 1|1 0 1 1 1 0 0|x x x x x| P P |1 0 0 t t i i i i|d d d d d| if (Pt) Rd=memw(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 0 0|x x x x x| P P |1 0 1 t t i i i i|d d d d d| if (!Pt) Rd=memw(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 0 0|x x x x x| P P |1 1 0 t t i i i i|d d d d d| if (Pt.new) Rd=memw(Rx++#s4:3) - LD/slot 0,1 +|1 0 0 1|1 0 1 1 1 0 0|x x x x x| P P |1 1 1 t t i i i i|d d d d d| if (!Pt.new) Rd=memw(Rx++#s4:3) - LD/slot 0,1 + +|1 0 0 1|1 1 1 1 1 0 0|i i i i i| P P |1 0 0 t t i 1 - -|d d d d d| if (Pt) Rd=memw(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 1 0 0|i i i i i| P P |1 0 1 t t i 1 - -|d d d d d| if (!Pt) Rd=memw(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 1 0 0|i i i i i| P P |1 1 0 t t i 1 - -|d d d d d| if (Pt.new) Rd=memw(#u6) - LD/slot 0,1 +|1 0 0 1|1 1 1 1 1 0 0|i i i i i| P P |1 1 1 t t i 1 - -|d d d d d| if (!Pt.new) Rd=memw(#u6) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 0 0 0 0 0 0|s s s s s| P P |0 - - - - - - - -|d d d d d| Rdd=deallocframe(Rs):raw - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 1 1 0 0 0 0|s s s s s| P P |0 0 0 0 - - - - -|d d d d d| Rdd=dealloc_return(Rs):raw - LD/slot 0 +|1 0 0 1|0 1 1 0 0 0 0|s s s s s| P P |0 0 1 0 v v - - -|d d d d d| if (Pv.new) Rdd=dealloc_return(Rs):nt:raw - LD/slot 0 +|1 0 0 1|0 1 1 0 0 0 0|s s s s s| P P |0 1 0 0 v v - - -|d d d d d| if (Pv) Rdd=dealloc_return(Rs):raw - LD/slot 0 +|1 0 0 1|0 1 1 0 0 0 0|s s s s s| P P |0 1 1 0 v v - - -|d d d d d| if (Pv.new) Rdd=dealloc_return(Rs):t:raw - LD/slot 0 +|1 0 0 1|0 1 1 0 0 0 0|s s s s s| P P |1 0 1 0 v v - - -|d d d d d| if (!Pv.new) Rdd=dealloc_return(Rs):nt:raw - LD/slot 0 +|1 0 0 1|0 1 1 0 0 0 0|s s s s s| P P |1 1 0 0 v v - - -|d d d d d| if (!Pv) Rdd=dealloc_return(Rs):raw - LD/slot 0 +|1 0 0 1|0 1 1 0 0 0 0|s s s s s| P P |1 1 1 0 v v - - -|d d d d d| if (!Pv.new) Rdd=dealloc_return(Rs):t:raw - LD/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 i i 0 0 0 1|s s s s s| P P |i i i i i i i i i|d d d d d| Rd=membh(Rs+#s11:1) - LD/slot 0,1 +|1 0 0 1|0 i i 0 0 1 1|s s s s s| P P |i i i i i i i i i|d d d d d| Rd=memubh(Rs+#s11:1) - LD/slot 0,1 +|1 0 0 1|0 i i 0 1 0 1|s s s s s| P P |i i i i i i i i i|d d d d d| Rdd=memubh(Rs+#s11:2) - LD/slot 0,1 +|1 0 0 1|0 i i 0 1 1 1|s s s s s| P P |i i i i i i i i i|d d d d d| Rdd=membh(Rs+#s11:2) - LD/slot 0,1 + +|1 0 0 1|1 0 0 0 0 0 1|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rd=membh(Rx++#s4:1:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 0 0 1|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rd=membh(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 0 1 1|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rd=memubh(Rx++#s4:1:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 0 1 1|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rd=memubh(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 1 0 1|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rdd=memubh(Rx++#s4:2:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 1 0 1|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rdd=memubh(Rx++I:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 1 1 1|x x x x x| P P |u 0 - - 0 i i i i|d d d d d| Rdd=membh(Rx++#s4:2:circ(Mu)) - LD/slot 0,1 +|1 0 0 1|1 0 0 0 1 1 1|x x x x x| P P |u 0 - - 1 - 0 - -|d d d d d| Rdd=membh(Rx++I:circ(Mu)) - LD/slot 0,1 + +|1 0 0 1|1 0 1 0 0 0 1|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rd=membh(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 0 0 1|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rd=membh(Rx++#s:4) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 0 1 1|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rd=memubh(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 0 1 1|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rd=memubh(Rx++#s:4) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 1 0 1|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rdd=memubh(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 1 0 1|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rdd=memubh(Rx++#s:4) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 1 1 1|e e e e e| P P |0 1 l l l l - l l|d d d d d| Rdd=membh(Re=#U6) - LD/slot 0,1 +|1 0 0 1|1 0 1 0 1 1 1|x x x x x| P P |0 0 - - - i i i i|d d d d d| Rdd=membh(Rx++#s:4) - LD/slot 0,1 + + +|1 0 0 1|1 1 0 0 0 0 1|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rd=membh(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 0 0 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=membh(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 0 1 1|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rd=memubh(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 0 1 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=memubh(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 1 0 1|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rdd=memubh(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 1 0 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=memubh(Rx++Mu) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 1 1 1|t t t t t| P P |i 1 l l l l i l l|d d d d d| Rdd=membh(Rt<<#u2+#U6) - LD/slot 0,1 +|1 0 0 1|1 1 0 0 1 1 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=membh(Rx++Mu) - LD/slot 0,1 + +|1 0 0 1|1 1 1 0 0 0 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=membh(Rx++Mu:brev) - LD/slot 0,1 +|1 0 0 1|1 1 1 0 0 1 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rd=memubh(Rx++Mu:brev) - LD/slot 0,1 +|1 0 0 1|1 1 1 0 1 0 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=memubh(Rx++Mu:brev) - LD/slot 0,1 +|1 0 0 1|1 1 1 0 1 1 1|x x x x x| P P |u 0 - - - - 0 - -|d d d d d| Rdd=membh(Rx++Mu:brev) - LD/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 1 1 0 - 0 0|s s s s s| P P |0 i i i i i i 0 0|t t t t t| memb(Rs+#u6:0)+=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 0 - 0 0|s s s s s| P P |0 i i i i i i 0 1|t t t t t| memb(Rs+#u6:0)-=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 0 - 0 0|s s s s s| P P |0 i i i i i i 1 0|t t t t t| memb(Rs+#u6:0)&=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 0 - 0 0|s s s s s| P P |0 i i i i i i 1 1|t t t t t| memb(Rs+#u6:0)|=Rt - MEMOP/slot 0 + +|0 0 1 1|1 1 1 1 - 0 0|s s s s s| P P |0 i i i i i i 0 0|l l l l l| memb(Rs+#u6:0)+=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 1 - 0 0|s s s s s| P P |0 i i i i i i 0 1|l l l l l| memb(Rs+#u6:0)-=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 1 - 0 0|s s s s s| P P |0 i i i i i i 1 0|l l l l l| memb(Rs+#u6:0)=clrbit(#U5) - MEMOP/slot 0 +|0 0 1 1|1 1 1 1 - 0 0|s s s s s| P P |0 i i i i i i 1 1|l l l l l| memb(Rs+#u6:0)=setbit(#U5) - MEMOP/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 1 1 0 - 0 1|s s s s s| P P |0 i i i i i i 0 0|t t t t t| memh(Rs+#u6:0)+=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 0 - 0 1|s s s s s| P P |0 i i i i i i 0 1|t t t t t| memh(Rs+#u6:0)-=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 0 - 0 1|s s s s s| P P |0 i i i i i i 1 0|t t t t t| memh(Rs+#u6:0)&=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 0 - 0 1|s s s s s| P P |0 i i i i i i 1 1|t t t t t| memh(Rs+#u6:0)|=Rt - MEMOP/slot 0 + +|0 0 1 1|1 1 1 1 - 0 1|s s s s s| P P |0 i i i i i i 0 0|l l l l l| memh(Rs+#u6:0)+=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 1 - 0 1|s s s s s| P P |0 i i i i i i 0 1|l l l l l| memh(Rs+#u6:0)-=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 1 - 0 1|s s s s s| P P |0 i i i i i i 1 0|l l l l l| memh(Rs+#u6:0)=clrbit(#U5) - MEMOP/slot 0 +|0 0 1 1|1 1 1 1 - 0 1|s s s s s| P P |0 i i i i i i 1 1|l l l l l| memh(Rs+#u6:0)=setbit(#U5) - MEMOP/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 1 1 0 - 1 0|s s s s s| P P |0 i i i i i i 0 0|t t t t t| memw(Rs+#u6:0)+=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 0 - 1 0|s s s s s| P P |0 i i i i i i 0 1|t t t t t| memw(Rs+#u6:0)-=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 0 - 1 0|s s s s s| P P |0 i i i i i i 1 0|t t t t t| memw(Rs+#u6:0)&=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 0 - 1 0|s s s s s| P P |0 i i i i i i 1 1|t t t t t| memw(Rs+#u6:0)|=Rt - MEMOP/slot 0 + +|0 0 1 1|1 1 1 1 - 1 0|s s s s s| P P |0 i i i i i i 0 0|l l l l l| memw(Rs+#u6:0)+=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 1 - 1 0|s s s s s| P P |0 i i i i i i 0 1|l l l l l| memw(Rs+#u6:0)-=Rt - MEMOP/slot 0 +|0 0 1 1|1 1 1 1 - 1 0|s s s s s| P P |0 i i i i i i 1 0|l l l l l| memw(Rs+#u6:0)=clrbit(#U5) - MEMOP/slot 0 +|0 0 1 1|1 1 1 1 - 1 0|s s s s s| P P |0 i i i i i i 1 1|l l l l l| memw(Rs+#u6:0)=setbit(#U5) - MEMOP/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 0|0 0 0 0 0 0 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(cmp.eq(Ns.new,Rt)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 0 0 0 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(cmp.eq(Ns.new,Rt)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 0 0 1 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(!cmp.eq(Ns.new,Rt)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 0 0 1 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(!cmp.eq(Ns.new,Rt)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 0 1 0 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(cmp.gt(Ns.new,Rt)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 0 1 0 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(cmp.gt(Ns.new,Rt)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 0 1 1 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(!cmp.gt(Ns.new,Rt)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 0 1 1 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(!cmp.gt(Ns.new,Rt)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 1 0 0 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(cmp.gtu(Ns.new,Rt)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 1 0 0 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(cmp.gtu(Ns.new,Rt)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 1 0 1 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(!cmp.gtu(Ns.new,Rt)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 1 0 1 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(!cmp.gtu(Ns.new,Rt)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 1 1 0 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(cmp.gt(Rt,Ns.new)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 1 1 0 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(cmp.gt(Rt,Ns.new)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 1 1 1 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(!cmp.gt(Rt,Ns.new)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 0 1 1 1 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(!cmp.gt(Rt,Ns.new)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 0 1 0 0 0 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(cmp.gtu(Rt,Ns.new)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 1 0 0 0 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(cmp.gtu(Rt,Ns.new)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 0 1 0 0 1 i i - s s s| P P |0 t t t t t i i i|i i i i -| if(!cmp.gtu(Rt,Ns.new)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 0 1 0 0 1 i i - s s s| P P |1 t t t t t i i i|i i i i -| if(!cmp.gtu(Rt,Ns.new)) jump:t #r9:2 - NV/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 0|0 1 0 0 0 0 i i - s s s| P P |0 l l l l l i i i|i i i i -| if (cmp.eq(Ns.new,#U5)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 0 0 0 i i - s s s| P P |1 l l l l l i i i|i i i i -| if (cmp.eq(Ns.new,#U5)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 0 0 1 i i - s s s| P P |0 l l l l l i i i|i i i i -| if (!cmp.eq(Ns.new,#U5)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 0 0 1 i i - s s s| P P |1 l l l l l i i i|i i i i -| if (!cmp.eq(Ns.new,#U5)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 0 1 0 i i - s s s| P P |0 l l l l l i i i|i i i i -| if (cmp.gt(Ns.new,#U5)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 0 1 0 i i - s s s| P P |1 l l l l l i i i|i i i i -| if (cmp.gt(Ns.new,#U5)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 0 1 1 i i - s s s| P P |0 l l l l l i i i|i i i i -| if (!cmp.gt(Ns.new,#U5)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 0 1 1 i i - s s s| P P |1 l l l l l i i i|i i i i -| if (!cmp.gt(Ns.new,#U5)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 1 0 0 i i - s s s| P P |0 l l l l l i i i|i i i i -| if (cmp.gtu(Ns.new,#U5)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 1 0 0 i i - s s s| P P |1 l l l l l i i i|i i i i -| if (cmp.gtu(Ns.new,#U5)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 1 0 1 i i - s s s| P P |0 l l l l l i i i|i i i i -| if (!cmp.gtu(Ns.new,#U5)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 1 0 1 i i - s s s| P P |1 l l l l l i i i|i i i i -| if (!cmp.gtu(Ns.new,#U5)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 1 1 0 i i - s s s| P P |0 - - - - - i i i|i i i i -| if (tstbit(Ns.new,#0)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 1 1 0 i i - s s s| P P |1 - - - - - i i i|i i i i -| if (tstbit(Ns.new,#0)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 1 1 1 i i - s s s| P P |0 - - - - - i i i|i i i i -| if (!tstbit(Ns.new,#0)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 0 1 1 1 i i - s s s| P P |1 - - - - - i i i|i i i i -| if (!tstbit(Ns.new,#0)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 1 0 0 0 i i - s s s| P P |0 - - - - - i i i|i i i i -| if (cmp.eq(Ns.new,#-1)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 1 0 0 0 i i - s s s| P P |1 - - - - - i i i|i i i i -| if (cmp.eq(Ns.new,#-1)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 1 0 0 1 i i - s s s| P P |0 - - - - - i i i|i i i i -| if (!cmp.eq(Ns.new,#-1)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 1 0 0 1 i i - s s s| P P |1 - - - - - i i i|i i i i -| if (!cmp.eq(Ns.new,#-1)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 1 0 1 0 i i - s s s| P P |0 - - - - - i i i|i i i i -| if (cmp.gt(Ns.new,#-1)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 1 0 1 0 i i - s s s| P P |1 - - - - - i i i|i i i i -| if (cmp.gt(Ns.new,#-1)) jump:t #r9:2 - NV/slot 0 +|0 0 1 0|0 1 1 0 1 1 i i - s s s| P P |0 - - - - - i i i|i i i i -| if (!cmp.gt(Ns.new,#-1)) jump:nt #r9:2 - NV/slot 0 +|0 0 1 0|0 1 1 0 1 1 i i - s s s| P P |1 - - - - - i i i|i i i i -| if (!cmp.gt(Ns.new,#-1)) jump:t #r9:2 - NV/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 1 1 0 1|s s s s s| P P |i u u u u u i - -|0 0 t t t| memb(Rs+Ru<<#u2)=Nt.new - NV ST/slot 0 +|0 1 0 0|1 i i 0 1 0 1|i i i i i| P P |i 0 0 t t t i i i|i i i i i| memb(gp+#u16:0)=Nt.new - NV ST/slot 0 +|1 0 1 0|0 i i 1 1 0 1|s s s s s| P P |i 0 0 t t t i i i|i i i i i| memb(Rs+#s11:0)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 0 1 1 0 1|x x x x x| P P |u 0 0 t t t 0 - -|- - - 1 -| memb(Rx++I:circ(Mu))=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 0 1 1 0 1|x x x x x| P P |u 0 0 t t t 0 i i|i i - 0 -| memb(Rx++#s4:0:circ(Mu))=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|e e e e e| P P |0 0 0 t t t 1 - l|l l l l l| memb(Re=#U6)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |0 0 0 t t t 0 i i|i i - 0 -| memb(Rx++#s4:0)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 1 0 1 1 0 1|u u u u u| P P |i 0 0 t t t 1 i l|l l l l l| memb(Ru<<#u2+#U6)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 1 0 1 1 0 1|x x x x x| P P |u 0 0 t t t 0 - -|- - - - -| memb(Rx++Mu)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|x x x x x| P P |u 0 0 t t t 0 - -|- - - - -| memb(Rx++Mu:brev)=Nt.new - NV ST/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 1 0 0 1 0 1|s s s s s| P P |i u u u u u i v v|0 0 t t t| if (Pv) memb(Rs+Ru<<#u2)=Nt.new - NV/slot 0 +|0 0 1 1|0 1 0 1 1 0 1|s s s s s| P P |i u u u u u i v v|0 0 t t t| if (!Pv) memb(Rs+Ru<<#u2)=Nt.new - NV/slot 0 +|0 0 1 1|0 1 1 0 1 0 1|s s s s s| P P |i u u u u u i v v|0 0 t t t| if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new - NV/slot 0 +|0 0 1 1|0 1 1 1 1 0 1|s s s s s| P P |i u u u u u i v v|0 0 t t t| if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new - NV/slot 0 + +|0 1 0 0|0 0 0 0 1 0 1|s s s s s| P P |i 0 0 t t t i i i|i i 0 v v| if (Pv) memb(Rs+#u6:0)=Nt.new - NV/slot 0 +|0 1 0 0|0 0 1 0 1 0 1|s s s s s| P P |i 0 0 t t t i i i|i i 0 v v| if (!Pv) memb(Rs+#u6:0)=Nt.new - NV/slot 0 +|0 1 0 0|0 1 0 0 1 0 1|s s s s s| P P |i 0 0 t t t i i i|i i 0 v v| if (Pv.new) memb(Rs+#u6:0)=Nt.new - NV/slot 0 +|0 1 0 0|0 1 1 0 1 0 1|s s s s s| P P |i 0 0 t t t i i i|i i 0 v v| if (!Pv.new) memb(Rs+#u6:0)=Nt.new - NV/slot 0 + +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 0 0 t t t 0 i i|i i 0 v v| if (Pv) memb(Rx++#s4:0)=Nt.new - NV/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 0 0 t t t 0 i i|i i 1 v v| if (!Pv) memb(Rx++#s4:0)=Nt.new - NV/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 0 0 t t t 1 i i|i i 0 v v| if (Pv.new) memb(Rx++#s4:0)=Nt.new - NV/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 0 0 t t t 1 i i|i i 1 v v| if (!Pv.new) memb(Rx++#s4:0)=Nt.new - NV/slot 0 + +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |0 0 0 t t t 1 i i|i i 0 v v| if (Pv) memb(#u6)=Nt.new - NV/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |0 0 0 t t t 1 i i|i i 1 v v| if (!Pv) memb(#u6)=Nt.new - NV/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |1 0 0 t t t 1 i i|i i 0 v v| if (Pv.new) memb(#u6)=Nt.new - NV/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |1 0 0 t t t 1 i i|i i 1 v v| if (!Pv.new) memb(#u6)=Nt.new - NV/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 1 1 0 1|s s s s s| P P |i u u u u u i - -|0 1 t t t| memh(Rs+Ru<<#u2)=Nt.new - NV ST/slot 0 +|0 1 0 0|1 i i 0 1 0 1|i i i i i| P P |i 0 1 t t t i i i|i i i i i| memh(gp+#u16:1)=Nt.new - NV ST/slot 0 +|1 0 1 0|0 i i 1 1 0 1|s s s s s| P P |i 0 1 t t t i i i|i i i i i| memh(Rs+#s11:1)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 0 1 1 0 1|x x x x x| P P |u 0 1 t t t 0 - -|- - - 1 -| memh(Rx++I:circ(Mu))=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 0 1 1 0 1|x x x x x| P P |u 0 1 t t t 0 i i|i i - 0 -| memh(Rx++#s4:1:circ(Mu))=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|e e e e e| P P |0 0 1 t t t 1 - l|l l l l l| memh(Re=#U6)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |0 0 1 t t t 0 i i|i i - 0 -| memh(Rx++#s4:1)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 1 0 1 1 0 1|u u u u u| P P |i 0 1 t t t 1 i l|l l l l l| memh(Ru<<#u2+#U6)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 1 0 1 1 0 1|x x x x x| P P |u 0 1 t t t 0 - -|- - - - -| memh(Rx++Mu)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|x x x x x| P P |u 0 1 t t t 0 - -|- - - - -| memh(Rx++Mu:brev)=Nt.new - NV ST/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 1 0 0 1 0 1|s s s s s| P P |i u u u u u i v v|0 1 t t t| if (Pv) memh(Rs+Ru<<#u2)=Nt.new - NV/slot 0 +|0 0 1 1|0 1 0 1 1 0 1|s s s s s| P P |i u u u u u i v v|0 1 t t t| if (!Pv) memh(Rs+Ru<<#u2)=Nt.new - NV/slot 0 +|0 0 1 1|0 1 1 0 1 0 1|s s s s s| P P |i u u u u u i v v|0 1 t t t| if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new - NV/slot 0 +|0 0 1 1|0 1 1 1 1 0 1|s s s s s| P P |i u u u u u i v v|0 1 t t t| if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new - NV/slot 0 + +|0 1 0 0|0 0 0 0 1 0 1|s s s s s| P P |i 0 1 t t t i i i|i i 0 v v| if (Pv) memh(Rs+#u6:1)=Nt.new - NV/slot 0 +|0 1 0 0|0 0 1 0 1 0 1|s s s s s| P P |i 0 1 t t t i i i|i i 0 v v| if (!Pv) memh(Rs+#u6:1)=Nt.new - NV/slot 0 +|0 1 0 0|0 1 0 0 1 0 1|s s s s s| P P |i 0 1 t t t i i i|i i 0 v v| if (Pv.new) memh(Rs+#u6:1)=Nt.new - NV/slot 0 +|0 1 0 0|0 1 1 0 1 0 1|s s s s s| P P |i 0 1 t t t i i i|i i 0 v v| if (!Pv.new) memh(Rs+#u6:1)=Nt.new - NV/slot 0 + +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 0 1 t t t 0 i i|i i 0 v v| if (Pv) memh(Rx++#s4:1)=Nt.new - NV/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 0 1 t t t 0 i i|i i 1 v v| if (!Pv) memh(Rx++#s4:1)=Nt.new - NV/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 0 1 t t t 1 i i|i i 0 v v| if (Pv.new) memh(Rx++#s4:1)=Nt.new - NV/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 0 1 t t t 1 i i|i i 1 v v| if (!Pv.new) memh(Rx++#s4:1)=Nt.new - NV/slot 0 + +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |0 0 1 t t t 1 i i|i i 0 v v| if (Pv) memh(#u6)=Nt.new - NV/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |0 0 1 t t t 1 i i|i i 1 v v| if (!Pv) memh(#u6)=Nt.new - NV/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |1 0 1 t t t 1 i i|i i 0 v v| if (Pv.new) memh(#u6)=Nt.new - NV/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |1 0 1 t t t 1 i i|i i 1 v v| if (!Pv.new) memh(#u6)=Nt.new - NV/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 1 1 0 1|s s s s s| P P |i u u u u u i - -|1 0 t t t| memw(Rs+Ru<<#u2)=Nt.new - NV ST/slot 0 +|0 1 0 0|1 i i 0 1 0 1|i i i i i| P P |i 1 0 t t t i i i|i i i i i| memw(gp+#u16:2)=Nt.new - NV ST/slot 0 +|1 0 1 0|0 i i 1 1 0 1|s s s s s| P P |i 1 0 t t t i i i|i i i i i| memw(Rs+#s11:2)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 0 1 1 0 1|x x x x x| P P |u 1 0 t t t 0 - -|- - - 1 -| memw(Rx++I:circ(Mu))=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 0 1 1 0 1|x x x x x| P P |u 1 0 t t t 0 i i|i i - 0 -| memw(Rx++#s4:2:circ(Mu))=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|e e e e e| P P |0 1 0 t t t 1 - l|l l l l l| memw(Re=#U6)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |0 1 0 t t t 0 i i|i i - 0 -| memw(Rx++#s4:2)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 1 0 1 1 0 1|u u u u u| P P |i 1 0 t t t 1 i l|l l l l l| memw(Ru<<#u2+#U6)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 1 0 1 1 0 1|x x x x x| P P |u 1 0 t t t 0 - -|- - - - -| memw(Rx++Mu)=Nt.new - NV ST/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|x x x x x| P P |u 1 0 t t t 0 - -|- - - - -| memw(Rx++Mu:brev)=Nt.new - NV ST/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 1 0 0 1 0 1|s s s s s| P P |i u u u u u i v v|1 0 t t t| if (Pv) memw(Rs+Ru<<#u2)=Nt.new - NV/slot 0 +|0 0 1 1|0 1 0 1 1 0 1|s s s s s| P P |i u u u u u i v v|1 0 t t t| if (!Pv) memw(Rs+Ru<<#u2)=Nt.new - NV/slot 0 +|0 0 1 1|0 1 1 0 1 0 1|s s s s s| P P |i u u u u u i v v|1 0 t t t| if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new - NV/slot 0 +|0 0 1 1|0 1 1 1 1 0 1|s s s s s| P P |i u u u u u i v v|1 0 t t t| if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new - NV/slot 0 + +|0 1 0 0|0 0 0 0 1 0 1|s s s s s| P P |i 1 0 t t t i i i|i i 0 v v| if (Pv) memw(Rs+#u6:2)=Nt.new - NV/slot 0 +|0 1 0 0|0 0 1 0 1 0 1|s s s s s| P P |i 1 0 t t t i i i|i i 0 v v| if (!Pv) memw(Rs+#u6:2)=Nt.new - NV/slot 0 +|0 1 0 0|0 1 0 0 1 0 1|s s s s s| P P |i 1 0 t t t i i i|i i 0 v v| if (Pv.new) memw(Rs+#u6:2)=Nt.new - NV/slot 0 +|0 1 0 0|0 1 1 0 1 0 1|s s s s s| P P |i 1 0 t t t i i i|i i 0 v v| if (!Pv.new) memw(Rs+#u6:2)=Nt.new - NV/slot 0 + +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 1 0 t t t 0 i i|i i 0 v v| if (Pv) memw(Rx++#s4:2)=Nt.new - NV/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 1 0 t t t 0 i i|i i 1 v v| if (!Pv) memw(Rx++#s4:2)=Nt.new - NV/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 1 0 t t t 1 i i|i i 0 v v| if (Pv.new) memw(Rx++#s4:2)=Nt.new - NV/slot 0 +|1 0 1 0|1 0 1 1 1 0 1|x x x x x| P P |1 1 0 t t t 1 i i|i i 1 v v| if (!Pv.new) memw(Rx++#s4:2)=Nt.new - NV/slot 0 + +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |0 1 0 t t t 1 i i|i i 0 v v| if (Pv) memw(#u6)=Nt.new - NV/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |0 1 0 t t t 1 i i|i i 1 v v| if (!Pv) memw(#u6)=Nt.new - NV/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |1 1 0 t t t 1 i i|i i 0 v v| if (Pv.new) memw(#u6)=Nt.new - NV/slot 0 +|1 0 1 0|1 1 1 1 1 0 1|- - - i i| P P |1 1 0 t t t 1 i i|i i 1 v v| if (!Pv.new) memw(#u6)=Nt.new - NV/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 1 1 1 0|s s s s s| P P |i u u u u u i - -|t t t t t| memd(Rs+Ru<<#u2)=Rtt - ST/slot 0,1 +|0 1 0 0|1 i i 0 1 1 0|i i i i i| P P |i t t t t t i i i|i i i i i| memd(gp+#u16:3)=Rtt - ST/slot 0,1 +|1 0 1 0|0 i i 1 1 1 0|s s s s s| P P |i t t t t t i i i|i i i i i| memd(Rs+#s11:3)=Rtt - ST/slot 0,1 +|1 0 1 0|1 0 0 1 1 1 0|x x x x x| P P |u t t t t t 0 - -|- - - 1 -| memd(Rx++I:circ(Mu))=Rtt - ST/slot 0,1 +|1 0 1 0|1 0 0 1 1 1 0|x x x x x| P P |u t t t t t 0 i i|i i - 0 -| memd(Rx++#s4:3:circ(Mu))=Rtt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 1 0|e e e e e| P P |0 t t t t t 1 - l|l l l l l| memd(Re=#U6)=Rtt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 1 0|x x x x x| P P |0 t t t t t 0 i i|i i - 0 -| memd(Rx++#s4:3)=Rtt - ST/slot 0,1 +|1 0 1 0|1 1 0 1 1 1 0|u u u u u| P P |i t t t t t 1 i l|l l l l l| memd(Ru<<#u2+#U6)=Rtt - ST/slot 0,1 +|1 0 1 0|1 1 0 1 1 1 0|x x x x x| P P |u t t t t t 0 - -|- - - - -| memd(Rx++Mu)=Rtt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 1 1 0|x x x x x| P P |u t t t t t 0 - -|- - - - -| memd(Rx++Mu:brev)=Rtt - ST/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 1 0|0 0 0 0 1 1 1|s s s s s| P P |0 t t t t t - - 0|0 1 0 d d| memd_rl(Rs):at=Rtt - ST/slot 0 +|1 0 1 0|0 0 0 0 1 1 1|s s s s s| P P |0 t t t t t - - 1|0 1 0 d d| memd_rl(Rs):st=Rtt - ST/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 1 0 0 1 1 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv) memd(Rs+Ru<<#u2)=Rtt - ST/slot 0,1 +|0 0 1 1|0 1 0 1 1 1 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv) memd(Rs+Ru<<#u2)=Rtt - ST/slot 0,1 +|0 0 1 1|0 1 1 0 1 1 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv.new) memd(Rs+Ru<<#u2)=Rtt - ST/slot 0,1 +|0 0 1 1|0 1 1 1 1 1 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt - ST/slot 0,1 + +|0 1 0 0|0 0 0 0 1 1 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv) memd(Rs+#u6:2)=Rtt - ST/slot 0,1 +|0 1 0 0|0 0 1 0 1 1 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv) memd(Rs+#u6:2)=Rtt - ST/slot 0,1 +|0 1 0 0|0 1 0 0 1 1 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv.new) memd(Rs+#u6:2)=Rtt - ST/slot 0,1 +|0 1 0 0|0 1 1 0 1 1 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv.new) memd(Rs+#u6:2)=Rtt - ST/slot 0,1 + +|1 0 1 0|1 0 1 1 1 1 0|x x x x x| P P |1 t t t t t 0 i i|i i 0 v v| if (Pv) memd(Rx++#s4:2)=Rtt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 1 0|x x x x x| P P |1 t t t t t 0 i i|i i 1 v v| if (!Pv) memd(Rx++#s4:2)=Rtt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 1 0|x x x x x| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memd(Rx++#s4:2)=Rtt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 1 0|x x x x x| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memd(Rx++#s4:2)=Rtt - ST/slot 0,1 + +|1 0 1 0|1 1 1 1 1 1 0|- - - i i| P P |0 t t t t t 1 i i|i i 0 v v| if (Pv) memd(#u6)=Rtt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 1 1 0|- - - i i| P P |0 t t t t t 1 i i|i i 1 v v| if (!Pv) memd(#u6)=Rtt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 1 1 0|- - - i i| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memd(#u6)=Rtt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 1 1 0|- - - i i| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memd(#u6)=Rtt - ST/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 1 1 0 0|s s s s s| P P |i u u u u u i - -|t t t t t| memb(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|1 1 0 - - 0 0|s s s s s| P P |l i i i i i i l l|l l l l l| memb(Rs+#u6:0)=#S8 - ST/slot 0,1 +|0 1 0 0|1 i i 0 1 0 0|i i i i i| P P |i t t t t t i i i|i i i i i| memb(gp+#u16:0)=Rt - ST/slot 0,1 +|1 0 1 0|0 i i 1 1 0 0|s s s s s| P P |i t t t t t i i i|i i i i i| memb(Rs+#s11:0)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 0 1 1 0 0|x x x x x| P P |u t t t t t 0 - -|- - - 1 -| memb(Rx++I:circ(Mu))=Rt - ST/slot 0,1 +|1 0 1 0|1 0 0 1 1 0 0|x x x x x| P P |u t t t t t 0 i i|i i - 0 -| memb(Rx++#s4:0:circ(Mu))=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 0 0|e e e e e| P P |0 t t t t t 1 - l|l l l l l| memb(Re=#U6)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 0 0|x x x x x| P P |0 t t t t t 0 i i|i i - 0 -| memb(Rx++#s4:0)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 0 1 1 0 0|u u u u u| P P |i t t t t t 1 i l|l l l l l| memb(Ru<<#u2+#U6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 0 1 1 0 0|x x x x x| P P |u t t t t t 0 - -|- - - - -| memb(Rx++Mu)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 1 0 0|x x x x x| P P |u t t t t t 0 - -|- - - - -| memb(Rx++Mu:brev)=Rt - ST/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 1 0 0 0 0 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv) memb(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 0 1 0 0 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv) memb(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 1 0 0 0 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv.new) memb(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 1 1 0 0 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv.new) memb(Rs+Ru<<#u2)=Rt - ST/slot 0,1 + +|0 0 1 1|1 0 0 0 0 0 0|s s s s s| P P |l i i i i i i v v|l l l l l| if (Pv) memb(Rs+#u6:0)=#S6 - ST/slot 0,1 +|0 0 1 1|1 0 0 0 1 0 0|s s s s s| P P |l i i i i i i v v|l l l l l| if (!Pv) memb(Rs+#u6:0)=#S6 - ST/slot 0,1 +|0 0 1 1|1 0 0 1 0 0 0|s s s s s| P P |l i i i i i i v v|l l l l l| if (Pv.new) memb(Rs+#u6:0)=#S6 - ST/slot 0,1 +|0 0 1 1|1 0 0 1 1 0 0|s s s s s| P P |l i i i i i i v v|l l l l l| if (!Pv.new) memb(Rs+#u6:0)=#S6 - ST/slot 0,1 + +|0 1 0 0|0 0 0 0 0 0 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv) memb(Rs+#u6:0)=Rt - ST/slot 0,1 +|0 1 0 0|0 0 1 0 0 0 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv) memb(Rs+#u6:0)=Rt - ST/slot 0,1 +|0 1 0 0|0 1 0 0 0 0 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv.new) memb(Rs+#u6:0)=Rt - ST/slot 0,1 +|0 1 0 0|0 1 1 0 0 0 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv.new) memb(Rs+#u6:0)=Rt - ST/slot 0,1 + +|1 0 1 0|1 0 1 1 0 0 0|x x x x x| P P |1 t t t t t 0 i i|i i 0 v v| if (Pv) memb(Rx++#s4:0)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 0 0|x x x x x| P P |1 t t t t t 0 i i|i i 1 v v| if (!Pv) memb(Rx++#s4:0)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 0 0|x x x x x| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memb(Rx++#s4:0)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 0 0|x x x x x| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memb(Rx++#s4:0)=Rt - ST/slot 0,1 + +|1 0 1 0|1 1 1 1 0 0 0|- - - i i| P P |0 t t t t t 1 i i|i i 0 v v| if (Pv) memb(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 0 0|- - - i i| P P |0 t t t t t 1 i i|i i 1 v v| if (!Pv) memb(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 0 0|- - - i i| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memb(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 0 0|- - - i i| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memb(#u6)=Rt - ST/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 1 0 1 0|s s s s s| P P |i u u u u u i - -|t t t t t| memh(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|1 0 1 1 0 1 1|s s s s s| P P |i u u u u u i - -|t t t t t| memh(Rs+Ru<<#u2)=Rt.H - ST/slot 0,1 +|0 0 1 1|1 1 0 - - 0 1|s s s s s| P P |l i i i i i i l l|l l l l l| memh(Rs+#u6:1)=#S8 - ST/slot 0,1 +|0 1 0 0|1 i i 0 0 1 0|i i i i i| P P |i t t t t t i i i|i i i i i| memh(gp+#u16:1)=Rt - ST/slot 0,1 +|0 1 0 0|1 i i 0 0 1 1|i i i i i| P P |i t t t t t i i i|i i i i i| memh(gp+#u16:1)=Rt.H - ST/slot 0,1 +|1 0 1 0|0 i i 1 0 1 0|s s s s s| P P |i t t t t t i i i|i i i i i| memh(Rs+#s11:1)=Rt - ST/slot 0,1 +|1 0 1 0|0 i i 1 0 1 1|s s s s s| P P |i t t t t t i i i|i i i i i| memh(Rs+#s11:1)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 0 0 1 0 1 0|x x x x x| P P |u t t t t t 0 - -|- - - 1 -| memh(Rx++I:circ(Mu))=Rt - ST/slot 0,1 +|1 0 1 0|1 0 0 1 0 1 0|x x x x x| P P |u t t t t t 0 i i|i i - 0 -| memh(Rx++#s4:1:circ(Mu))=Rt - ST/slot 0,1 +|1 0 1 0|1 0 0 1 0 1 1|x x x x x| P P |u t t t t t 0 - -|- - - 1 -| memh(Rx++I:circ(Mu))=Rt.H - ST/slot 0,1 +|1 0 1 0|1 0 0 1 0 1 1|x x x x x| P P |u t t t t t 0 i i|i i - 0 -| memh(Rx++#s4:1:circ(Mu))=Rt.H - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 0|e e e e e| P P |0 t t t t t 1 - l|l l l l l| memh(Re=#U6)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 0|x x x x x| P P |0 t t t t t 0 i i|i i - 0 -| memh(Rx++#s4:1)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 1|e e e e e| P P |0 t t t t t 1 - l|l l l l l| memh(Re=#U6)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 1|x x x x x| P P |0 t t t t t 0 i i|i i - 0 -| memh(Rx++#s4:1)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 1 0 1 0 1 0|u u u u u| P P |i t t t t t 1 i l|l l l l l| memh(Ru<<#u2+#U6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 0 1 0 1 0|x x x x x| P P |u t t t t t 0 - -|- - - - -| memh(Rx++Mu)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 0 1 0 1 1|u u u u u| P P |i t t t t t 1 i l|l l l l l| memh(Ru<<#u2+#U6)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 1 0 1 0 1 1|x x x x x| P P |u t t t t t 0 - -|- - - - -| memh(Rx++Mu)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 1 0|x x x x x| P P |u t t t t t 0 - -|- - - - -| memh(Rx++Mu:brev)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 1 1|x x x x x| P P |u t t t t t 0 - -|- - - - -| memh(Rx++Mu:brev)=Rt.H - ST/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 1 0 0 0 1 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv) memh(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 0 0 0 1 1|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv) memh(Rs+Ru<<#u2)=Rt.H - ST/slot 0,1 +|0 0 1 1|0 1 0 1 0 1 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv) memh(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 0 1 0 1 1|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv) memh(Rs+Ru<<#u2)=Rt.H - ST/slot 0,1 +|0 0 1 1|0 1 1 0 0 1 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv.new) memh(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 1 0 0 1 1|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv.new) memh(Rs+Ru<<#u2)=Rt.H - ST/slot 0,1 +|0 0 1 1|0 1 1 1 0 1 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv.new) memh(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 1 1 0 1 1|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv.new) memh(Rs+Ru<<#u2)=Rt.H - ST/slot 0,1 + +|0 0 1 1|1 0 0 0 0 0 1|s s s s s| P P |l i i i i i i v v|l l l l l| if (Pv) memh(Rs+#u6:1)=#S6 - ST/slot 0,1 +|0 0 1 1|1 0 0 0 1 0 1|s s s s s| P P |l i i i i i i v v|l l l l l| if (!Pv) memh(Rs+#u6:1)=#S6 - ST/slot 0,1 +|0 0 1 1|1 0 0 1 0 0 1|s s s s s| P P |l i i i i i i v v|l l l l l| if (Pv.new) memh(Rs+#u6:1)=#S6 - ST/slot 0,1 +|0 0 1 1|1 0 0 1 1 0 1|s s s s s| P P |l i i i i i i v v|l l l l l| if (!Pv.new) memh(Rs+#u6:1)=#S6 - ST/slot 0,1 + +|0 1 0 0|0 0 0 0 0 1 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv) memh(Rs+#u6:1)=Rt - ST/slot 0,1 +|0 1 0 0|0 0 0 0 0 1 1|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv) memh(Rs+#u6:1)=Rt.H - ST/slot 0,1 +|0 1 0 0|0 0 1 0 0 1 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv) memh(Rs+#u6:1)=Rt - ST/slot 0,1 +|0 1 0 0|0 0 1 0 0 1 1|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv) memh(Rs+#u6:1)=Rt.H - ST/slot 0,1 +|0 1 0 0|0 1 0 0 0 1 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv.new) memh(Rs+#u6:1)=Rt - ST/slot 0,1 +|0 1 0 0|0 1 0 0 0 1 1|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv.new) memh(Rs+#u6:1)=Rt.H - ST/slot 0,1 +|0 1 0 0|0 1 1 0 0 1 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv.new) memh(Rs+#u6:1)=Rt - ST/slot 0,1 +|0 1 0 0|0 1 1 0 0 1 1|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv.new) memh(Rs+#u6:1)=Rt.H - ST/slot 0,1 + +|1 0 1 0|1 0 1 1 0 1 0|x x x x x| P P |1 t t t t t 0 i i|i i 0 v v| if (Pv) memh(Rx++#s4:1)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 0|x x x x x| P P |1 t t t t t 0 i i|i i 1 v v| if (!Pv) memh(Rx++#s4:1)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 0|x x x x x| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memh(Rx++#s4:1)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 0|x x x x x| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memh(Rx++#s4:1)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 1|x x x x x| P P |1 t t t t t 0 i i|i i 0 v v| if (Pv) memh(Rx++#s4:1)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 1|x x x x x| P P |1 t t t t t 0 i i|i i 1 v v| if (!Pv) memh(Rx++#s4:1)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 1|x x x x x| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memh(Rx++#s4:1)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 0 1 1 0 1 1|x x x x x| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memh(Rx++#s4:1)=Rt.H - ST/slot 0,1 + +|1 0 1 0|1 1 1 1 0 1 0|- - - i i| P P |0 t t t t t 1 i i|i i 0 v v| if (Pv) memh(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 1 0|- - - i i| P P |0 t t t t t 1 i i|i i 1 v v| if (!Pv) memh(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 1 0|- - - i i| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memh(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 1 0|- - - i i| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memh(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 1 1|- - - i i| P P |0 t t t t t 1 i i|i i 0 v v| if (Pv) memh(#u6)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 1 1|- - - i i| P P |0 t t t t t 1 i i|i i 1 v v| if (!Pv) memh(#u6)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 1 1|- - - i i| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memh(#u6)=Rt.H - ST/slot 0,1 +|1 0 1 0|1 1 1 1 0 1 1|- - - i i| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memh(#u6)=Rt.H - ST/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 1 0|0 0 0 0 0 1 1|s s s s s| P P |0 t t t t t - - 0|0 1 1 d d| release(Rs):at - ST/slot 0 +|1 0 1 0|0 0 0 0 0 1 1|s s s s s| P P |0 t t t t t - - 1|0 1 1 d d| release(Rs):st - ST/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|1 0 1 1 1 0 0|s s s s s| P P |i u u u u u i - -|t t t t t| memw(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|1 1 0 - - 1 0|s s s s s| P P |l i i i i i i l l|l l l l l| memw(Rs+#u6:2)=#S8 - ST/slot 0,1 +|0 1 0 0|1 i i 0 1 0 0|i i i i i| P P |i t t t t t i i i|i i i i i| memw(gp+#u16:2)=Rt - ST/slot 0,1 +|1 0 1 0|0 i i 1 1 0 0|s s s s s| P P |i t t t t t i i i|i i i i i| memw(Rs+#s11:2)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 0 1 1 0 0|x x x x x| P P |u t t t t t 0 - -|- - - 1 -| memw(Rx++I:circ(Mu))=Rt - ST/slot 0,1 +|1 0 1 0|1 0 0 1 1 0 0|x x x x x| P P |u t t t t t 0 i i|i i - 0 -| memw(Rx++#s4:2:circ(Mu))=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 0 0|e e e e e| P P |0 t t t t t 1 - l|l l l l l| memw(Re=#U6)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 0 0|x x x x x| P P |0 t t t t t 0 i i|i i - 0 -| memw(Rx++#s4:2)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 0 1 1 0 0|u u u u u| P P |i t t t t t 1 i l|l l l l l| memw(Ru<<#u2+#U6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 0 1 1 0 0|x x x x x| P P |u t t t t t 0 - -|- - - - -| memw(Rx++Mu)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 1 0 0|x x x x x| P P |u t t t t t 0 - -|- - - - -| memw(Rx++Mu:brev)=Rt - ST/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 1 0|0 0 0 0 1 0 1|s s s s s| P P |- t t t t t - - 0|0 1 0 d d| memw_rl(Rs):at=Rt - ST/slot 0 +|1 0 1 0|0 0 0 0 1 0 1|s s s s s| P P |- t t t t t - - 1|0 1 0 d d| memw_rl(Rs):st=Rt - ST/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 0 1 1|0 1 0 0 1 0 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv) memw(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 0 1 1 0 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv) memw(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 1 0 1 0 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (Pv.new) memw(Rs+Ru<<#u2)=Rt - ST/slot 0,1 +|0 0 1 1|0 1 1 1 1 0 0|s s s s s| P P |i u u u u u i v v|t t t t t| if (!Pv.new) memw(Rs+Ru<<#u2)=Rt - ST/slot 0,1 + +|0 0 1 1|1 0 0 0 0 1 0|s s s s s| P P |l i i i i i i v v|l l l l l| if (Pv) memw(Rs+#u6:2)=#S6 - ST/slot 0,1 +|0 0 1 1|1 0 0 0 1 1 0|s s s s s| P P |l i i i i i i v v|l l l l l| if (!Pv) memw(Rs+#u6:2)=#S6 - ST/slot 0,1 +|0 0 1 1|1 0 0 1 0 1 0|s s s s s| P P |l i i i i i i v v|l l l l l| if (Pv.new) memw(Rs+#u6:2)=#S6 - ST/slot 0,1 +|0 0 1 1|1 0 0 1 1 1 0|s s s s s| P P |l i i i i i i v v|l l l l l| if (!Pv.new) memw(Rs+#u6:2)=#S6 - ST/slot 0,1 + +|0 1 0 0|0 0 0 0 1 0 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv) memw(Rs+#u6:2)=Rt - ST/slot 0,1 +|0 1 0 0|0 0 1 0 1 0 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv) memw(Rs+#u6:2)=Rt - ST/slot 0,1 +|0 1 0 0|0 1 0 0 1 0 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (Pv.new) memw(Rs+#u6:2)=Rt - ST/slot 0,1 +|0 1 0 0|0 1 1 0 1 0 0|s s s s s| P P |i t t t t t i i i|i i 0 v v| if (!Pv.new) memw(Rs+#u6:2)=Rt - ST/slot 0,1 + +|1 0 1 0|1 0 1 1 1 0 0|x x x x x| P P |1 t t t t t 0 i i|i i 0 v v| if (Pv) memw(Rx++#s4:2)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 0 0|x x x x x| P P |1 t t t t t 0 i i|i i 1 v v| if (!Pv) memw(Rx++#s4:2)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 0 0|x x x x x| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memw(Rx++#s4:2)=Rt - ST/slot 0,1 +|1 0 1 0|1 0 1 1 1 0 0|x x x x x| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memw(Rx++#s4:2)=Rt - ST/slot 0,1 + +|1 0 1 0|1 1 1 1 1 0 0|- - - i i| P P |0 t t t t t 1 i i|i i 0 v v| if (Pv) memw(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 1 0 0|- - - i i| P P |0 t t t t t 1 i i|i i 1 v v| if (!Pv) memw(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 1 0 0|- - - i i| P P |1 t t t t t 1 i i|i i 0 v v| if (Pv.new) memw(#u6)=Rt - ST/slot 0,1 +|1 0 1 0|1 1 1 1 1 0 0|- - - i i| P P |1 t t t t t 1 i i|i i 1 v v| if (!Pv.new) memw(#u6)=Rt - ST/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 1 0|0 0 0 0 1 0 0|x x x x x| P P |0 0 0 i i i i i i|i i i i i| allocframe(Rx,#u11:3):raw - ST/slot 0,1 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 0 1 0 0 0 0|s s s s s| P P |0 0 0 - - - 0 0 0|d d d d d| Rd=memw_locked(Rs) - SYSTEM/slot 0 +|1 0 0 1|0 0 1 0 0 0 0|s s s s s| P P |0 1 0 - - - 0 0 0|d d d d d| Rdd=memw_locked(Rs) - SYSTEM/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 0 0 0 1 0 1|s s s s s| P P |- t t t t t - - -|- 0 0 d d| memw_locked(Rs,Pd)=Rt - SYSTEM/slot 0 +|1 0 0 1|0 0 0 0 1 1 1|s s s s s| P P |0 t t t t t - - -|- 0 0 d d| memd_locked(Rs,Pd)=Rtt - SYSTEM/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 1 0|0 0 0 0 1 1 0|s s s s s| P P |0 - - - - - - - -|- - - - -| dczeroa(Rs) - SYSTEM/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 1 0|1 0 0 0 0 0 0|- - - - -| P P |- - - - - - 0 0 0|- - - - -| barrier - SYSTEM/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 0|1 1 0 0 0 0 1|- - - - -| P P |- - - - - - 0 0 0|- - - - -| barrier - SYSTEM/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 0 1|0 1 0 0 0 0 0|s s s s s| P P |0 - - i i i i i i|i i i i i| dcfetch(Rs+#u11:3) - SYSTEM/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|1 0 1 0|0 0 0 0 0 0 0|s s s s s| P P |- - - - - - - - -|- - - - -| dccleana(Rs) - SYSTEM/slot 0 +|1 0 1 0|0 0 0 0 0 0 1|s s s s s| P P |- - - - - - - - -|- - - - -| dcinva(Rs) - SYSTEM/slot 0 +|1 0 1 0|0 0 0 0 0 1 0|s s s s s| P P |- - - - - - - - -|- - - - -| dccleaninva(Rs) - SYSTEM/slot 0 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 1 0|0 0 1 0 0 1 0|s s s s s| P P |- - - - - - 0 0 1|- - - - -| diag(Rs) - SYSTEM/slot 3 +|0 1 1 0|0 0 1 0 0 1 0|s s s s s| P P |- t t t t t 0 1 0|- - - - -| diag0(Rss,Rtt) - SYSTEM/slot 3 +|0 1 1 0|0 0 1 0 0 1 0|s s s s s| P P |- t t t t t 0 1 1|- - - - -| diag1(Rss,Rtt) - SYSTEM/slot 3 +|ICLASS |P MajOp MinOp|s5 |Parse| |d5 | +|0 1 0 1|0 1 1 0 1 1 0|s s s s s| P P |0 0 0 - - - - - -|- - - - -| icinva(Rs) - SYSTEM/slot 2 +|0 1 0 1|0 1 1 1 1 1 0|0 0 0 0 0| P P |0 - - - 0 0 0 0 0|0 0 0 1 0| isync - SYSTEM/slot 2 +|1 0 1 0|0 1 1 0 0 0 0|s s s s s| P P |- t t t t t 0 0 0|- - - - -| l2fetch(Rs,Rt) - SYSTEM/slot 0 +|1 0 1 0|0 1 1 0 1 0 0|s s s s s| P P |- t t t t t - - -|- - - - -| l2fetch(Rs,Rtt) - SYSTEM/slot 0 +|0 1 0 1|0 1 0 0 0 1 -|- - - i i| P P |- i i i i i - - -|i i i - -| pause(#u10) - SYSTEM/slot 2 +|1 0 1 0|1 0 0 0 0 0 0|- - - - -| P P |- - - - - 0 1 1 1|d d d d d| Rd=dmsyncht - SYSTEM/slot 0 +|1 0 1 0|1 0 0 0 0 1 0|- - - - -| P P |- - - - - - - - -|- - - - -| syncht - SYSTEM/slot 0 +|0 1 1 0|0 0 1 0 0 1 0|s s s s s| P P |- - - - - - 0 0 0|- - - - -| trace(Rs) - SYSTEM/slot 3 +|0 1 0 1|0 1 0 0 0 0 -|- - - - -| P P |- i i i i i - - -|i i i - -| trap0(#u8) - SYSTEM/slot 2 +|0 1 0 1|0 1 0 0 1 0 -|x x x x x| P P |- i i i i i - - -|i i i - -| trap1(Rx,#u8) - SYSTEM/slot 2 +|0 1 0 1|0 1 1 1 1 1 1|x x x x x| P P |0 1 - - - - 0 0 0|- - - - -| unpause - SYSTEM/slot 2 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 0 0 0|0 0 0 0|1 0 0|s s s s s| P P |- - - - - -|1 1 0|- - - - -| Rdd=abs(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|1 0 0|s s s s s| P P |- - - - - -|1 0 0|d d d d d| Rd=abs(Rs) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|1 0 0|s s s s s| P P |- - - - - -|1 0 1|d d d d d| Rd=abs(Rs) - XTYPE ALU/slot 2,3 + +|1 1 0 1|1 0 1 1|0 i i|s s s s s| P P |i d d d d d|i i i|u u u u u| Rd=add(Rs,add(Ru,#s6)) - XTYPE ALU/slot 2,3 +|1 1 0 1|1 0 1 1|1 i i|s s s s s| P P |i d d d d d|i i i|u u u u u| Rd=add(Rs,sub(#s6,Ru)) - XTYPE ALU/slot 2,3 +|1 1 1 0|0 0 1 0|0 - -|s s s s s| P P |0 i i i i i|i i i|x x x x x| Rx+=add(Rs,#s8) - XTYPE ALU/slot 2,3 +|1 1 1 0|0 0 1 0|1 - -|s s s s s| P P |0 i i i i i|i i i|x x x x x| Rx-=add(Rs,#s8) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|0 0 0|s s s s s| P P |0 t t t t t|0 0 1|x x x x x| Rx+=add(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|1 0 0|s s s s s| P P |0 t t t t t|0 0 1|x x x x x| Rx-=add(Rs,Rt) - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 0 1|0 0 1 1|0 0 0|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rdd=add(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 1|s s s s s| P P |- t t t t t|1 0 1|d d d d d| Rdd=add(Rss,Rtt):sat - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 1|s s s s s| P P |- t t t t t|1 1 0|d d d d d| Rdd=add(Rss,Rtt):raw:lo - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 1|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rdd=add(Rss,Rtt):raw:hi - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|1 0 0|s s s s s| P P |- t t t t t|0 - -|d d d d d| Rd=add(Rs,Rt):sat:deprecated - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 0 1|0 1 0 1|0 0 0|s s s s s| P P |- t t t t t|0 0 -|d d d d d| Rd=add(Rt.L,Rs.L) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 0|s s s s s| P P |- t t t t t|0 1 -|d d d d d| Rd=add(Rt.L,Rs.H) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 0|s s s s s| P P |- t t t t t|1 0 -|d d d d d| Rd=add(Rt.L,Rs.L):sat - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 0|s s s s s| P P |- t t t t t|1 1 -|d d d d d| Rd=add(Rt.L,Rs.H):sat - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 1 0|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rd=add(Rt.L,Rs.L):<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 1 0|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rd=add(Rt.L,Rs.H):<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 1 0|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rd=add(Rt.H,Rs.L):<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 1 0|s s s s s| P P |- t t t t t|0 1 1|d d d d d| Rd=add(Rt.H,Rs.H):<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 1 0|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rd=add(Rt.L,Rs.L):sat:<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 1 0|s s s s s| P P |- t t t t t|1 0 1|d d d d d| Rd=add(Rt.L,Rs.H):sat:<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 1 0|s s s s s| P P |- t t t t t|1 1 0|d d d d d| Rd=add(Rt.H,Rs.L):sat:<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 1 0|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rd=add(Rt.H,Rs.H):sat:<<16 - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 0 0|0 0 1 0|1 1 0|s s s s s| P P |- t t t t t|- x x|d d d d d| Rdd=add(Rss,Rtt,Px):carry - XTYPE ALU/slot 2,3 +|1 1 0 0|0 0 1 0|1 1 1|s s s s s| P P |- t t t t t|- x x|d d d d d| Rdd=sub(Rss,Rtt,Px):carry - XTYPE ALU/slot 2,3 +|1 0 0 0|1 0 0 0|1 1 0|s s s s s| P P |0 i i i i i|1 0 1|d d d d d| Rd=clip(Rs,#u5) - XTYPE ALU/slot 2,3 - only on a core with Hexagon audio extensions +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 0 0 0|0 0 0 0|1 0 0|s s s s s| P P |- - - - - -|1 0 0|d d d d d| Rdd=not(Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 1|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rdd=and(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 1|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rdd=and(Rss,~Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 1|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=or(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 1|s s s s s| P P |- t t t t t|0 1 1|d d d d d| Rdd=or(Rss,~Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 1|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rdd=xor(Rss,Rtt) - XTYPE ALU/slot 2,3 + +|1 1 0 0|1 0 1 0|1 0 -|s s s s s| P P |0 t t t t t|0 0 0|x x x x x| Rxx^=xor(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|1 0 1 0|0 0 i|s s s s s| P P |i i i i i i|i i i|x x x x x| Rx|=and(Rs,#s10) - XTYPE ALU/slot 2,3 +|1 1 0 1|1 0 1 0|0 1 i|x x x x x| P P |i i i i i i|i i i|u u u u u| Rx=or(Ru,and(Rx,#s10)) - XTYPE ALU/slot 2,3 +|1 1 0 1|1 0 1 0|1 0 i|s s s s s| P P |i i i i i i|i i i|x x x x x| Rx|=or(Rs,#s10) - XTYPE ALU/slot 2,3 + +|1 1 1 0|1 1 1 1|0 0 1|s s s s s| P P |0 t t t t t|0 0 0|x x x x x| Rx|=and(Rs,~Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|0 0 1|s s s s s| P P |0 t t t t t|0 0 1|x x x x x| Rx&=and(Rs,~Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|0 0 1|s s s s s| P P |0 t t t t t|0 1 0|x x x x x| Rx^=and(Rs,~Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|0 1 0|s s s s s| P P |0 t t t t t|0 0 0|x x x x x| Rx&=and(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|0 1 0|s s s s s| P P |0 t t t t t|0 0 1|x x x x x| Rx&=or(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|0 1 0|s s s s s| P P |0 t t t t t|0 1 0|x x x x x| Rx&=xor(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|0 1 0|s s s s s| P P |0 t t t t t|0 1 1|x x x x x| Rx|=and(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|1 0 0|s s s s s| P P |0 t t t t t|0 1 1|x x x x x| Rx^=xor(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|1 1 0|s s s s s| P P |0 t t t t t|0 0 0|x x x x x| Rx|=or(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|1 1 0|s s s s s| P P |0 t t t t t|0 0 1|x x x x x| Rx|=xor(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|1 1 0|s s s s s| P P |0 t t t t t|0 1 0|x x x x x| Rx^=and(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|1 1 0|s s s s s| P P |0 t t t t t|0 1 1|x x x x x| Rx^=or(Rs,Rt) - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 0 1|0 1 0 1|1 1 0|s s s s s| P P |- t t t t t|0 - -|d d d d d| Rd=max(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|1 1 0|s s s s s| P P |- t t t t t|1 - -|d d d d d| Rd=maxu(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 0|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rdd=max(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 0|s s s s s| P P |- t t t t t|1 0 1|d d d d d| Rdd=maxu(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|1 0 1|s s s s s| P P |- t t t t t|0 - -|d d d d d| Rd=min(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|1 0 1|s s s s s| P P |- t t t t t|1 - -|d d d d d| Rd=minu(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 1|s s s s s| P P |- t t t t t|1 1 0|d d d d d| Rdd=min(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 1|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rdd=minu(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 1|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rd=modwrap(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 0 0 0|0 0 0 0|1 0 0|s s s s s| P P |- - - - - -|1 0 1|d d d d d| Rdd=neg(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|1 0 0|s s s s s| P P |- - - - - -|1 1 0|d d d d d| Rd=neg(Rs):sat - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 0 0 0|1 0 0 0|1 1 0|s s s s s| P P |- - - - - -|0 0 1|d d d d d| Rd=round(Rss):sat - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|1 1 1|s s s s s| P P |0 i i i i i|0 0 -|d d d d d| Rd=cround(Rs,#u5) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|1 1 1|s s s s s| P P |0 i i i i i|1 0 -|d d d d d| Rd=round(Rs,#u5) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|1 1 1|s s s s s| P P |0 i i i i i|1 0 -|d d d d d| Rd=round(Rs,#u5):sat - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|1 1 1|s s s s s| P P |i i i i i i|0 1 -|d d d d d| Rdd=cround(Rss,#u6) - XTYPE ALU/slot 2,3 + +|1 1 0 0|0 1 1 0|1 1 -|s s s s s| P P |- t t t t t|0 0 -|d d d d d| Rd=cround(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 0 0|0 1 1 0|1 1 -|s s s s s| P P |- t t t t t|1 0 -|d d d d d| Rdd=round(Rss,Rt) - XTYPE ALU/slot 2,3 +|1 1 0 0|0 1 1 0|1 1 -|s s s s s| P P |- t t t t t|1 0 -|d d d d d| Rd=round(Rs,Rt) - XTYPE ALU/slot 2,3 +|1 1 0 0|0 1 1 0|1 1 -|s s s s s| P P |- t t t t t|0 1 -|d d d d d| Rd=cround(Rs,Rt):sat - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 0 1|0 0 1 1|0 0 1|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rdd=sub(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|1 0 0|s s s s s| P P |- t t t t t|1 - -|d d d d d| Rd=sub(Rt,Rs):sat:deprecated - XTYPE ALU/slot 2,3 +|1 1 1 0|1 1 1 1|0 0 0|s s s s s| P P |0 t t t t t|0 1 1|x x x x x| Rx+=sub(Rt,Rs) - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|0 0 -|d d d d d| Rd=sub(Rt.L,Rs.L) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|0 1 -|d d d d d| Rd=sub(Rt.L,Rs.H) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|1 0 -|d d d d d| Rd=sub(Rt.L,Rs.L):sat - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|1 1 -|d d d d d| Rd=sub(Rt.L,Rs.H):sat - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rd=sub(Rt.L,Rs.L):<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rd=sub(Rt.L,Rs.H):<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rd=sub(Rt.H,Rs.L):<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|0 1 1|d d d d d| Rd=sub(Rt.H,Rs.H):<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rd=sub(Rt.L,Rs.L):sat:<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|1 0 1|d d d d d| Rd=sub(Rt.L,Rs.H):sat:<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|1 1 0|d d d d d| Rd=sub(Rt.H,Rs.L):sat:<<16 - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|0 0 1|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rd=sub(Rt.H,Rs.H):sat:<<16 - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 0 0 0|0 0 0 0|0 1 0|s s s s s| P P |- - - - - -|1 0 0|d d d d d| Rdd=vabsh(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|0 0 0 0|0 1 0|s s s s s| P P |- - - - - -|1 0 1|d d d d d| Rdd=vabsh(Rss):sat - XTYPE ALU/slot 2,3 +|1 0 0 0|0 0 0 0|0 1 0|s s s s s| P P |- - - - - -|1 1 0|d d d d d| Rdd=vabsw(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|0 0 0 0|0 1 0|s s s s s| P P |- - - - - -|1 1 1|d d d d d| Rdd=vabsw(Rss):sat - XTYPE ALU/slot 2,3 +|1 1 1 0|1 0 0 0|1 0 1|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rdd=vabsdiffub(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 0 0 0|1 1 1|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rdd=vabsdiffb(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 0 0 0|0 1 1|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rdd=vabsdiffh(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 0 0 0|0 0 1|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rdd=vabsdiffw(Rtt,Rss) - XTYPE ALU/slot 2,3 + +|1 1 1 0|1 0 1 0|1 0 1|s s s s s| P P |0 t t t t t|0 e e|x x x x x| Rxx,Pe=vacsh(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 0 0|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=vaddh(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 0 0|s s s s s| P P |- t t t t t|0 1 1|d d d d d| Rdd=vaddh(Rss,Rtt):sat - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 0 0|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rdd=vadduh(Rss,Rtt):sat - XTYPE ALU/slot 2,3 +|1 1 0 0|0 0 0 1|0 1 -|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rd=vaddhub(Rss,Rtt):sat - XTYPE ALU/slot 2,3 + +|1 1 1 0|1 0 0 0|0 1 0|s s s s s| P P |0 t t t t t|0 0 1|d d d d d| Rdd=vraddub(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 0 1 0|0 1 0|s s s s s| P P |0 t t t t t|0 0 1|x x x x x| Rxx+=vraddub(Rss,Rtt) - XTYPE ALU/slot 2,3 + +|1 1 1 0|1 0 0 1|0 - -|s s s s s| P P |0 t t t t t|- 0 1|d d d d d| Rd=vradduh(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 0 0 1|0 - 1|s s s s s| P P |0 t t t t t|1 1 1|d d d d d| Rd=vraddh(Rss,Rtt) - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|0 0 0|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rdd=vaddub(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 0 0|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rdd=vaddub(Rss,Rtt):sat - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|0 0 0|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rdd=vaddw(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 0 0|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rdd=vaddw(Rss,Rtt):sat - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|0 1 0|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=vavgh(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 0|s s s s s| P P |- t t t t t|0 1 1|d d d d d| Rdd=vavgh(Rss,Rtt):rnd - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 0|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rdd=vavgh(Rss,Rtt):crnd - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 0|s s s s s| P P |- t t t t t|1 0 1|d d d d d| Rdd=vavguh(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 0|s s s s s| P P |- t t t t t|1 1 -|d d d d d| Rdd=vavguh(Rss,Rtt):rnd - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 0|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rdd=vnavgh(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 0|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rdd=vnavgh(Rtt,Rss):rnd:sat - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 0|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=vnavgh(Rtt,Rss):crnd:sat - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|0 1 0|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rdd=vavgub(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 0|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rdd=vavgub(Rss,Rtt):rnd - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|0 1 1|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rdd=vavgw(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 1|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rdd=vavgw(Rss,Rtt):rnd - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 1|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=vavgw(Rss,Rtt):crnd - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 1|s s s s s| P P |- t t t t t|0 1 1|d d d d d| Rdd=vavguw(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 1 1|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rdd=vavguw(Rss,Rtt):rnd - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 0|s s s s s| P P |- t t t t t|0 1 1|d d d d d| Rdd=vnavgw(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 0|s s s s s| P P |- t t t t t|1 0 -|d d d d d| Rdd=vnavgw(Rtt,Rss):rnd:sat - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 0|s s s s s| P P |- t t t t t|1 1 -|d d d d d| Rdd=vnavgw(Rtt,Rss):crnd:sat - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 0 0 0|1 0 0 0|1 1 0|s s s s s| P P |0 i i i i i|1 1 0|d d d d d| Rdd=vclip(Rss,#u5) - XTYPE ALU/slot 2,3 - only on a core with Hexagon audio extensions +|1 0 0 0|0 0 1 1|1 1 -|s s s s s| P P |- t t t t t|0 1 -|d d d d d| Rdd=vcnegh(Rss,Rt) - XTYPE ALU/slot 2,3 +|1 0 0 0|0 0 1 1|0 0 1|s s s s s| P P |1 t t t t t|1 1 1|x x x x x| Rxx+=vrcnegh(Rss,Rt) - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|1 1 0|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rdd=vmaxub(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 0|s s s s s| P P |- t t t t t|1 1 0|d d d d d| Rdd=vmaxb(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 0|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rdd=vmaxh(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 0|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=vmaxuh(Rtt,Rss) - XTYPE ALU/slot 2,3 + +|1 1 0 0|1 0 1 1|0 0 1|s s s s s| P P |0 t t t t t|0 0 1|u u u u u| Rxx=vrmaxh(Rss,Ru) - XTYPE ALU/slot 2,3 +|1 1 0 0|1 0 1 1|0 0 1|s s s s s| P P |1 t t t t t|0 0 1|u u u u u| Rxx=vrmaxuh(Rss,Ru) - XTYPE ALU/slot 2,3 + +|1 1 0 0|1 0 1 1|0 0 1|s s s s s| P P |0 x x x x x|0 1 0|u u u u u| Rxx=vrmaxw(Rss,Ru) - XTYPE ALU/slot 2,3 +|1 1 0 0|1 0 1 1|0 0 1|s s s s s| P P |1 x x x x x|0 1 0|u u u u u| Rxx=vrmaxuw(Rss,Ru) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 1|s s s s s| P P |- t t t t t|1 0 1|d d d d d| Rdd=vmaxuw(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 0|s s s s s| P P |- t t t t t|0 1 1|d d d d d| Rdd=vmaxw(Rtt,Rss) - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 0 1|0 0 1 1|1 0 1|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rdd=vminub(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 1 0|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rdd=vminb(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 0 1 0|1 1 1|s s s s s| P P |0 t t t t t|0 e e|d d d d d| Rdd,Pe=vminub(Rtt,Rss) - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|1 0 1|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rdd=vminh(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 1|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=vminuh(Rtt,Rss) - XTYPE ALU/slot 2,3 + +|1 1 0 0|1 0 1 1|0 0 1|s s s s s| P P |0 x x x x x|1 0 1|u u u u u| Rxx=vrminh(Rss,Ru) - XTYPE ALU/slot 2,3 +|1 1 0 0|1 0 1 1|0 0 1|s s s s s| P P |1 x x x x x|1 0 1|u u u u u| Rxx=vrminuh(Rss,Ru) - XTYPE ALU/slot 2,3 + +|1 1 0 0|1 0 1 1|0 0 1|s s s s s| P P |0 x x x x x|1 1 0|u u u u u| Rxx=vrminw(Rss,Ru) - XTYPE ALU/slot 2,3 +|1 1 0 0|1 0 1 1|0 0 1|s s s s s| P P |1 x x x x x|1 1 0|u u u u u| Rxx=vrminuw(Rss,Ru) - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|1 0 1|s s s s s| P P |- x x x x x|0 1 1|d d d d d| Rdd=vminw(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|1 0 1|s s s s s| P P |- x x x x x|1 0 0|d d d d d| Rdd=vminuw(Rtt,Rss) - XTYPE ALU/slot 2,3 + +|1 1 1 0|1 0 0 0|0 1 0|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=vrsadub(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 1 0|1 0 1 0|0 1 0|s s s s s| P P |- t t t t t|0 1 0|x x x x x| Rxx+=vrsadub(Rss,rtt) - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|0 0 1|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=vsubh(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 0 1|s s s s s| P P |- t t t t t|0 1 1|d d d d d| Rdd=vsubh(Rtt,Rss):sat - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 0 1|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rdd=vsubuh(Rtt,Rss):sat - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|0 0 1|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rdd=vsubub(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 0 1|s s s s s| P P |- t t t t t|0 0 1|d d d d d| Rdd=vsubub(Rtt,Rss):sat - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 1 1|0 0 1|s s s s s| P P |- t t t t t|1 0 1|d d d d d| Rdd=vsubw(Rtt,Rss) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 0 1 1|0 0 1|s s s s s| P P |- t t t t t|1 1 0|d d d d d| Rdd=vsubw(Rtt,Rss):sat - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 0 0 0|1 0 0 0|0 1 0|s s s s s| P P |- - - - - -|0 0 0|d d d d d| Rd=clb(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 0 0 0|0 1 0|s s s s s| P P |- - - - - -|0 1 0|d d d d d| Rd=cl0(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 0 0 0|0 1 0|s s s s s| P P |- - - - - -|1 0 0|d d d d d| Rd=cl1(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 0 0 0|0 1 1|s s s s s| P P |- - - - - -|0 0 0|d d d d d| Rd=normamt(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 0 0 0|0 1 1|s s s s s| P P |i i i i i i|0 1 0|d d d d d| Rd=add(clb(Rss),#s6) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|0 0 1|s s s s s| P P |i i i i i i|0 0 0|d d d d d| Rd=add(clb(Rs),#s6) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|0 0 0|s s s s s| P P |- - - - - -|1 0 0|d d d d d| Rd=clb(Rs) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|0 0 0|s s s s s| P P |- - - - - -|1 0 1|d d d d d| Rd=cl0(Rs) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|0 0 0|s s s s s| P P |- - - - - -|1 1 0|d d d d d| Rd=cl1(Rs) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|0 0 0|s s s s s| P P |- - - - - -|1 1 1|d d d d d| Rd=normamt(Rs) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 0 0 0|0 1 1|s s s s s| P P |- - - - - -|0 1 1|d d d d d| Rd=popcount(Rss) - XTYPE ALU/slot 2,3 + +|1 0 0 0|1 0 0 0|1 1 1|s s s s s| P P |- - - - - -|0 1 0|d d d d d| Rd=ct0(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 0 0 0|1 1 1|s s s s s| P P |- - - - - -|1 0 0|d d d d d| Rd=ct1(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|0 1 0|s s s s s| P P |- - - - - -|1 0 0|d d d d d| Rd=ct0(Rs) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|0 1 0|s s s s s| P P |- - - - - -|1 0 1|d d d d d| Rd=ct1(Rs) - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 0 0 0|0 0 0 1|l l l|s s s s s| P P |i i i i i i|l l l|d d d d d| Rdd=extractu(Rss,#u6,#U6) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 0 1 0|l l l|s s s s s| P P |i i i i i i|l l l|d d d d d| Rdd=extract(Rss,#u6,#U6) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 1|0 l l|s s s s s| P P |0 i i i i i|l l l|d d d d d| Rd=extractu(Rs,#u5,#U5) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 1|1 l l|s s s s s| P P |0 i i i i i|l l l|d d d d d| Rd=extract(Rs,#u5,#U5) - XTYPE ALU/slot 2,3 + +|1 1 0 0|0 0 0 1|0 0 -|s s s s s| P P |- t t t t t|0 0 -|d d d d d| Rdd=extractu(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 0|0 0 0 1|1 1 -|s s s s s| P P |- t t t t t|1 0 -|d d d d d| Rdd=extractu(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 0|1 0 0 1|1 1 -|s s s s s| P P |- t t t t t|0 0 -|d d d d d| Rd=extractu(Rs,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 0|1 0 0 1|1 1 -|s s s s s| P P |- t t t t t|0 1 -|d d d d d| Rd=extract(Rs,Rtt) - XTYPE ALU/slot 2,3 + +|1 0 0 0|0 0 1 1|l l l|s s s s s| P P |i i i i i i|l l l|x x x x x| Rxx=insert(Rss,#u6,#U6) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 1 1|0 l l|s s s s s| P P |0 i i i i i|l l l|x x x x x| Rx=insert(Rs,#u5,#U5) - XTYPE ALU/slot 2,3 +|1 1 0 0|1 0 0 0|- - -|s s s s s| P P |- t t t t t|- - -|x x x x x| Rx=insert(Rs,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 0|1 0 1 0|0 - -|s s s s s| P P |0 t t t t t|- - -|x x x x x| Rxx=insert(Rss,Rtt) - XTYPE ALU/slot 2,3 + +|1 0 0 0|0 0 0 0|1 1 0|s s s s s| P P |- - - - - -|1 0 0|d d d d d| Rdd=deinterleave(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|0 0 0 0|1 1 0|s s s s s| P P |- - - - - -|1 0 1|d d d d d| Rdd=interleave(Rss) - XTYPE ALU/slot 2,3 +|1 1 0 0|0 0 0 1|1 0 -|s s s s s| P P |- t t t t t|1 1 0|d d d d d| Rdd=lfs(Rss,Rtt) - XTYPE ALU/slot 2,3 + +|1 1 0 1|0 0 0 0|- - -|s s s s s| P P |- t t t t t|- - -|d d d d d| Rd=parity(Rss,Rtt) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 1|1 1 1|s s s s s| P P |- t t t t t|- - -|d d d d d| Rd=parity(Rs,Rt) - XTYPE ALU/slot 2,3 + +|1 0 0 0|0 0 0 0|1 1 0|s s s s s| P P |- - - - - -|1 1 0|d d d d d| Rdd=brev(Rss) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|0 1 0|s s s s s| P P |- - - - - -|1 1 0|d d d d d| Rd=brev(Rs) - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 0 0 0|1 1 0 0|1 1 0|s s s s s| P P |0 i i i i i|0 0 0|d d d d d| Rd=setbit(Rs,#u5) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|1 1 0|s s s s s| P P |0 i i i i i|0 0 1|d d d d d| Rd=clrbit(Rs,#u5) - XTYPE ALU/slot 2,3 +|1 0 0 0|1 1 0 0|1 1 0|s s s s s| P P |0 i i i i i|0 1 0|d d d d d| Rd=togglebit(Rs,#u5) - XTYPE ALU/slot 2,3 + +|1 0 0 0|1 0 0 0|1 1 0|s s s s s| P P |0 i i i i i|1 0 0|d d d d d| Rdd=bitsplit(Rs,#u5) - XTYPE ALU/slot 2,3 +|1 1 0 1|0 1 0 0|- - 1|s s s s s| P P |- t t t t t|- - -|d d d d d| Rdd=bitsplit(Rs,Rt) - XTYPE ALU/slot 2,3 + +|1 0 0 0|0 1 1 1|0 0 i|s s s s s| P P |l l l l l l|i i i|x x x x x| Rx=tableidxb(Rs,#u4,#S6):raw - XTYPE ALU/slot 2,3 +|1 0 0 0|0 1 1 1|0 1 i|s s s s s| P P |l l l l l l|i i i|x x x x x| Rx=tableidxh(Rs,#u4,#S6):raw - XTYPE ALU/slot 2,3 +|1 0 0 0|0 1 1 1|1 0 i|s s s s s| P P |l l l l l l|i i i|x x x x x| Rx=tableidxw(Rs,#u4,#S6):raw - XTYPE ALU/slot 2,3 +|1 0 0 0|0 1 1 1|1 1 i|s s s s s| P P |l l l l l l|i i i|x x x x x| Rx=tableidxd(Rs,#u4,#S6):raw - XTYPE ALU/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 0 0|0 0 0 1|0 1 -|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rdd=vxaddsubh(Rss,Rtt):sat - XTYPE COMPLEX/slot 2,3 +|1 1 0 0|0 0 0 1|0 1 -|s s s s s| P P |- t t t t t|1 1 0|d d d d d| Rdd=vxsubaddh(Rss,Rtt):sat - XTYPE COMPLEX/slot 2,3 +|1 1 0 0|0 0 0 1|1 1 -|s s s s s| P P |- t t t t t|0 0 -|d d d d d| Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat - XTYPE COMPLEX/slot 2,3 +|1 1 0 0|0 0 0 1|1 1 -|s s s s s| P P |- t t t t t|0 1 -|d d d d d| Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat - XTYPE COMPLEX/slot 2,3 + +|1 1 0 0|0 0 0 1|0 1 -|s s s s s| P P |- t t t t t|0 0 0|d d d d d| Rdd=vxaddsubh(Rss,Rtt):sat - XTYPE COMPLEX/slot 2,3 +|1 1 0 0|0 0 0 1|0 1 -|s s s s s| P P |- t t t t t|0 1 0|d d d d d| Rdd=vxsubaddh(Rss,Rtt):sat - XTYPE COMPLEX/slot 2,3 + +|1 1 1 0|0 1 0 1|N 0 0|s s s s s| P P |0 t t t t t|1 1 0|d d d d d| Rdd=cmpy(Rs,Rt)[:<<N]:sat - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|0 1 0 1|N 1 0|s s s s s| P P |0 t t t t t|1 1 0|d d d d d| Rdd=cmpy(Rs,Rt*)[:<<N]:sat - XTYPE COMPLEX/slot 2,3 + +|1 1 1 0|0 1 1 1|N 0 0|s s s s s| P P |0 t t t t t|1 1 0|x x x x x| Rxx+=cmpy(Rs,Rt)[:<<N]:sat - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|0 1 1 1|N 0 0|s s s s s| P P |0 t t t t t|1 1 1|x x x x x| Rxx-=cmpy(Rs,Rt)[:<<N]:sat - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|0 1 1 1|N 1 0|s s s s s| P P |0 t t t t t|1 1 0|x x x x x| Rxx+=cmpy(Rs,Rt*)[:<<N]:sat - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|0 1 1 1|N 1 0|s s s s s| P P |0 t t t t t|1 1 1|x x x x x| Rxx-=cmpy(Rs,Rt*)[:<<N]:sat - XTYPE COMPLEX/slot 2,3 + +|1 1 1 0|0 1 0 1|0 0 0|s s s s s| P P |0 t t t t t|0 0 1|d d d d d| Rdd=cmpyi(Rs,Rt) - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|0 1 0 1|0 0 0|s s s s s| P P |0 t t t t t|0 1 0|d d d d d| Rdd=cmpyr(Rs,Rt) - XTYPE COMPLEX/slot 2,3 + +|1 1 1 0|0 1 1 1|0 0 0|s s s s s| P P |0 t t t t t|0 0 1|x x x x x| Rxx+=cmpyi(Rs,Rt) - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|0 1 1 1|0 0 0|s s s s s| P P |0 t t t t t|0 1 0|x x x x x| Rxx+=cmpyr(Rs,Rt) - XTYPE COMPLEX/slot 2,3 + +|1 1 1 0|1 1 0 1|N 0 1|s s s s s| P P |0 t t t t t|1 1 0|d d d d d| Rd=cmpy(Rs,Rt)[:<<N]:rnd:sat - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 1 0 1|N 1 1|s s s s s| P P |0 t t t t t|1 1 0|d d d d d| Rd=cmpy(Rs,Rt*)[:<<N]:rnd:sat - XTYPE COMPLEX/slot 2,3 + +|1 1 0 0|0 1 0 1|- - -|s s s s s| P P |- t t t t t|1 0 0|d d d d d| Rd=cmpyiwh(Rss,Rt):<<1:rnd:sat - XTYPE COMPLEX/slot 2,3 +|1 1 0 0|0 1 0 1|- - -|s s s s s| P P |- t t t t t|1 0 1|d d d d d| Rd=cmpyiwh(Rss,Rt*):<<1:rnd:sat - XTYPE COMPLEX/slot 2,3 +|1 1 0 0|0 1 0 1|- - -|s s s s s| P P |- t t t t t|1 1 0|d d d d d| Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat - XTYPE COMPLEX/slot 2,3 +|1 1 0 0|0 1 0 1|- - -|s s s s s| P P |- t t t t t|1 1 1|d d d d d| Rd=cmpyrwh(Rss,Rt*):<<1:rnd:sat - XTYPE COMPLEX/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 1 0|1 0 0 0|0 1 1|s s s s s| P P |0 t t t t t|0 1 0|d d d d d| Rdd=cmpyiw(Rss,Rtt) - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 0 0|1 0 0|s s s s s| P P |0 t t t t t|0 1 0|d d d d d| Rdd=cmpyrw(Rss,Rtt) - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 0 0|1 1 0|s s s s s| P P |0 t t t t t|0 1 0|d d d d d| Rdd=cmpyrw(Rss,Rtt*) - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 0 0|1 1 1|s s s s s| P P |0 t t t t t|0 1 0|d d d d d| Rdd=cmpyiw(Rss,Rtt*) - XTYPE COMPLEX/slot 2,3 + +|1 1 1 0|1 0 0 1|0 0 0|s s s s s| P P |0 t t t t t|1 0 0|d d d d d| Rd=cmpyiw(Rss,Rtt*):<<1:sat - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 0 1|0 0 1|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rd=cmpyiw(Rss,Rtt):<<1:sat - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 0 1|0 1 0|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rd=cmpyrw(Rss,Rtt):<<1:sat - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 0 1|0 1 1|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rd=cmpyrw(Rss,Rtt*):<<1:sat - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 0 1|1 0 0|s s s s s| P P |0 t t t t t|1 0 0|d d d d d| Rd=cmpyiw(Rss,Rtt*):<<1:rnd:sat - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 0 1|1 0 1|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rd=cmpyiw(Rss,Rtt):<<1:rnd:sat - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 0 1|1 1 0|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rd=cmpyrw(Rss,Rtt):<<1:rnd:sat - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 0 1|1 1 1|s s s s s| P P |0 t t t t t|0 0 0|d d d d d| Rd=cmpyrw(Rss,Rtt*):<<1:rnd:sat - XTYPE COMPLEX/slot 3 + +|1 1 1 0|1 0 1 0|0 1 0|s s s s s| P P |0 t t t t t|1 1 0|x x x x x| Rxx+cmpyiw(Rss,Rtt*) - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 1 0|0 1 1|s s s s s| P P |0 t t t t t|0 1 0|x x x x x| Rxx+cmpyiw(Rss,Rtt) - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 1 0|1 0 0|s s s s s| P P |0 t t t t t|0 1 0|x x x x x| Rxx+cmpyrw(Rss,Rtt) - XTYPE COMPLEX/slot 3 +|1 1 1 0|1 0 1 0|1 1 0|s s s s s| P P |0 t t t t t|0 1 0|x x x x x| Rxx+cmpyrw(Rss,Rtt*) - XTYPE COMPLEX/slot 3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 1 0|1 0 0 0|N 0 1|s s s s s| P P |0 t t t t t|1 1 0|d d d d d| Rdd=vcmpyr(Rss,Rtt)[:<<N]:sat - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 0 0|N 1 0|s s s s s| P P |0 t t t t t|1 1 0|d d d d d| Rdd=vcmpyi(Rss,Rtt)[:<<N]:sat - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 1 0|0 0 1|s s s s s| P P |0 t t t t t|1 0 0|x x x x x| Rxx+=vcmpyr(Rss,Rtt):sat - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 1 0|0 0 1|s s s s s| P P |0 t t t t t|1 0 0|x x x x x| Rxx+=vcmpyr(Rss,Rtt):sat - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 1 0|0 1 0|s s s s s| P P |0 t t t t t|1 0 0|x x x x x| Rxx+=vcmpyi(Rss,Rtt):sat - XTYPE COMPLEX/slot 2,3 +|1 0 0 0|0 0 0 0|1 0 0|s s s s s| P P |- - - - - -|1 1 1|d d d d d| Rdd=vconj(Rss):sat - XTYPE COMPLEX/slot 2,3 +|1 1 0 0|0 0 1 1|1 1 -|s s s s s| P P |- t t t t t|0 0 -|d d d d d| Rdd=vcrotate(Rss,Rt) - XTYPE COMPLEX/slot 2,3 + +|1 1 1 0|1 0 0 0|1 0 1|s s s s s| P P |0 t t t t t|1 0 0|d d d d d| Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:hi - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 0 0|1 1 1|s s s s s| P P |0 t t t t t|1 0 0|d d d d d| Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:lo - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 1 0|1 0 1|s s s s s| P P |0 t t t t t|1 0 0|x x x x x| Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:hi - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 1 0|1 1 1|s s s s s| P P |0 t t t t t|1 0 0|x x x x x| Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:lo - XTYPE COMPLEX/slot 2,3 + +|1 1 1 0|1 0 0 1|1 - 1|s s s s s| P P |0 t t t t t|1 1 0|d d d d d| Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:hi - XTYPE COMPLEX/slot 2,3 +|1 1 1 0|1 0 0 1|1 - 1|s s s s s| P P |0 t t t t t|1 1 1|d d d d d| Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:lo - XTYPE COMPLEX/slot 2,3 + +|1 1 0 0|0 0 1 1|1 1 -|s s s s s| P P |i t t t t t|1 1 i|d d d d d| Rdd=vrcrotate(Rss,Rt,#u2) - XTYPE COMPLEX/slot 2,3 +|1 1 0 0|1 0 1 1|1 0 1|s s s s s| P P |i t t t t t|- - i|x x x x x| Rxx+=vrcrotate(Rss,Rt,#u2) - XTYPE COMPLEX/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | +|1 1 1 0|1 0 0 0|0 0 0|s s s s s| P P |0 t t t t t|0 1 1|d d d d d| Rdd=dfadd(Rss,Rtt) - XTYPE FP/slot 2,3 +|1 1 1 0|1 0 1 1|0 0 0|s s s s s| P P |0 t t t t t|0 1 1|d d d d d| Rd=sfadd(Rs,Rt) - XTYPE FP/slot 2,3 + +|1 0 0 0|0 1 0 1|1 1 1|s s s s s| P P |0 i i i i i|- - -|- - d d d| Pd=sfclass(Rs,#u5) - XTYPE FP/slot 2,3 +|1 1 0 1|1 1 0 0|1 0 0|s s s s s| P P |- 0 0 0 i i|i i i|1 0 - d d| Pd=dfclass(Rss,#u5) - XTYPE FP/slot 2,3 +|ICLASS |RegType|MajOp|s5 |Parse| |MinOp|d5 | diff --git a/src/display.rs b/src/display.rs new file mode 100644 index 0000000..d84807d --- /dev/null +++ b/src/display.rs @@ -0,0 +1,7 @@ +use core::fmt; + +use crate::{Opcode, Operand}; + +impl fmt::Display for Opcode { + +} diff --git a/src/lib.rs b/src/lib.rs new file mode 100644 index 0000000..aa7bbb1 --- /dev/null +++ b/src/lib.rs @@ -0,0 +1,934 @@ +//! qualcomm `hexagon` decoder implemented as part of the `yaxpeax` project. implements traits +//! provided by `yaxpeax-arch`. +//! +//! decoder is written against the ISA described in `Qualcomm Hexagon V73`: +//! * retrieved 2024-09-21 from https://docs.qualcomm.com/bundle/publicresource/80-N2040-53_REV_AB_Qualcomm_Hexagon_V73_Programmers_Reference_Manual.pdf +//! * sha256: `44ebafd1119f725bd3c6ffb87499232520df9a0a6e3e3dc6ea329b15daed11a8` + +use core::fmt; +use core::cmp; + +use yaxpeax_arch::{AddressDiff, Arch, Decoder, LengthedInstruction, Reader}; +use yaxpeax_arch::StandardDecodeError as DecodeError; + +#[derive(Debug)] +pub struct Hexagon; + +impl Arch for Hexagon { + type Word = u8; + /// V73 Section 3.3.7: + /// > Packets should not wrap the *4GB address space*. + type Address = u32; + type Instruction = InstructionPacket; + type DecodeError = yaxpeax_arch::StandardDecodeError; + type Decoder = InstDecoder; + type Operand = Operand; +} + +#[derive(Debug, Copy, Clone, Default)] +struct Predicate { + state: u8, +} + +impl Predicate { + fn reg(num: u8) -> Self { + assert!(num <= 0b11); + Self { state: num } + } + + fn num(&self) -> u8 { + self.state & 0b11 + } + + fn set_negated(mut self) -> Self { + assert!(self.state & 0b0100 == 0); + self.state |= 0b0100; + self + } + + fn negated(&self) -> bool { + self.state & 0b0100 != 0 + } + + fn set_pred_new(mut self) -> Self { + assert!(self.state & 0b1000 == 0); + self.state |= 0b1000; + self + } + + fn pred_new(&self) -> bool { + self.state & 0b1000 != 0 + } +} + +#[derive(Debug, Copy, Clone, Default)] +struct LoopEnd { + loops_ended: u8 +} + +impl LoopEnd { + fn end_0(&self) -> bool { + self.loops_ended & 0b01 != 0 + } + + fn end_1(&self) -> bool { + self.loops_ended & 0b10 != 0 + } + + fn end_any(&self) -> bool { + self.loops_ended != 0 + } + + /// NOT FOR PUBLIC + fn mark_end(&mut self, lp: u8) { + self.loops_ended |= 1 << lp; + } +} + +/// V73 Section 3.3.3: +/// > The assembler automatically rejects packets that oversubscribe the hardware resources. +/// +/// but such bit patterns may exist. invalid packets likely mean the disassembler has walked into +/// invalid code, but should be decoded and shown as-is; the application using `yaxpeax-hexagon` +/// must decide what to do with bogus instruction packets. +#[derive(Debug, Copy, Clone, Default)] +pub struct InstructionPacket { + /// each packet has up to four instructions (V73 Section 1.1.3) + instructions: [Instruction; 4], + /// the actual number of instructions in this packet + instruction_count: u8, + /// the number of 4-byte instruction words this packet occupies + word_count: u8, + /// how this packet interacts with hardware loops 0 and/or 1 + loop_effect: LoopEnd, +} + +impl fmt::Display for InstructionPacket { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.write_str("{ ")?; + write!(f, "{}", self.instructions[0]); + for i in 1..self.instruction_count { + write!(f, "; {}", self.instructions[i as usize])?; + } + + f.write_str(" }")?; + if self.loop_effect.end_0() { + f.write_str(":endloop0")?; + } + if self.loop_effect.end_1() { + f.write_str(":endloop1")?; + } + + Ok(()) + } +} + +/// V5x Section 1.7.2 describes register access syntax. paraphrased: +/// +/// registers may be written as `Rds[.elst]`. +/// +/// `ds` describes the operand type and bit size: +/// | Symbol | Operand Type | Size (in Bits) | +/// |--------|--------------|----------------| +/// | d | Destination | 32 | +/// | dd | Destination | 64 | +/// | s | Source 1 | 32 | +/// | ss | Source 1 | 64 | +/// | t | Source 2 | 32 | +/// | tt | Source 2 | 64 | +/// | u | Source 3 | 32 | +/// | uu | Source 3 | 64 | +/// | x | Source+Dest | 32 | +/// | xx | Source+Dest | 64 | +/// +/// `elst` describes access of the bit fields in register `Rds`. V5x Figure 1-4: +/// +/// ``` +/// | .b[7] | .b[6] | .b[5] | .b[4] | .b[3] | .b[2] | .b[1] | .b[0] | signed bytes +/// | .ub[7] | .ub[6] | .ub[5] | .ub[4] | .ub[3] | .ub[2] | .ub[1] | .ub[0] | unsigned bytes +/// | .h[3] | .h[2] | .h[1] | .h[0] | signed halfwords +/// | .uh[3] | .uh[2] | .uh[1] | .uh[0] | unsigned halfwords +/// | .w[1] | .w[0] | signed words +/// | .uw[1] | .uw[0] | unsigned words +/// ``` +/// +/// meanwhile a register can be accessed as a single element with some trailing specifiers. V5x +/// Table 1-2: +/// +/// | Symbol | Meaning | +/// |--------|---------| +/// | .sN | Bits `[N-1:0]` are treated as an N-bit signed number. For example, R0.s16 means the least significant 16 bits of R0 are treated as a 16-bit signed number. | +/// | .uN | Bits `[N-1:0]` are treated as an N-bit unsigned number. | +/// | .H | The most significant 16 bits of a 32-bit register. | +/// | .L | The least significant 16 bits of a 32-bit register. | +/// +/// and finally, "Duplex instructions" (V73 Section 3.6): +/// > Unlike Compound instructions, duplex instructions do not have distinctive syntax – in +/// > assembly code they appear identical to the instructions they are composed of. The assembler +/// > is responsible for recognizing when a pair of instructions can be encoded as a single duplex +/// > rather than a pair of regular instruction words. +/// +/// V73 Section 10.3 discusses duplex instructions in more detail: +/// > A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00. The sub-instructions +/// > that comprise a duplex are encoded as 13-bit fields in the duplex. +/// > +/// > The sub-instructions in a duplex always execute in slot 0 and slot 1. +#[derive(Debug, Copy, Clone)] +pub struct Instruction { + opcode: Opcode, + dest: Option<Operand>, + predicate: Option<Predicate>, + sources: [Operand; 3], + sources_count: u8, +} + +/// V73 Section 3.1 indicates that jumps have taken/not-taken hints, saturation can be a hint, +/// rounding can be a hint, predicate can be used for carry in/out, result shifting by fixed +/// counts, and load/store reordering prevention are all kinds of hints that may be present. +/// +/// additionally, V73 Section 3.2 outlines instruction classes which relate to the available +/// execution units: +/// ``` +/// XTYPE +/// XTYPE ALU 64-bit ALU operations +/// XTYPE BIT Bit operations +/// XTYPE COMLPEX +/// XTYPE FP +/// XTYPE MPY +/// XTYPE PERM Vector permut and format conversion +/// XTYPE PRED Predicate operations +/// XTYPE SHIFT Shift operations (with optional ALU) +/// ALU32 32-bit ALU operations +/// ALU32 ALU Arithmetic and logical +/// ALU32 PERM Permute +/// ALU32 PRED Predicate operations +/// CR +/// JR +/// J +/// LD +/// MEMOP +/// NV +/// NV J +/// NV ST +/// ST +/// SYSTEM +/// SYSTEM USER +/// ``` +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum Opcode { + /// TODO: remove. should never be shown. implies an instruction was parially decoded but + /// accepted? + BUG, + // V73 Section 10.9 + // > NOTE: When a constant extender is explicitly specified with a GP-relative load/store, the + // > processor ignores the value in GP and creates the effective address directly from the 32-bit + // > constant value. + // + // TODO: similar special interpretation of constant extender on 32-bit immediate operands and + // 32-bit jump/call target addresses. + + Nop, + + // V73 page 214 ("Jump to address") + Jump, + + Memb, + Memub, + Memh, + Memuh, + Memw, + Memd, + + Membh, + MemhFifo, + Memubh, + MembFifo, + + Aslh, + Asrh, + Mov, + Zxtb, + Sxtb, + Zxth, + Sxth, +} + +/// TODO: don't know if this will be useful, but this is how V73 is described.. it also appears to +/// be the overall structure of the processor at least back to V5x. +/// TODO: how far back does this organization reflect reality? all the way to V2? +enum ExecutionUnit { + /// Load/store unit + /// LD, ST, ALU32, MEMOP, NV, SYSTEM + S0, + /// Load/store unit + /// LD, ST, ALU32 + S1, + /// X unit + /// XTYPE, ALU32, J, JR + S2, + /// X unit + /// XTYPE, ALU32, J, CR + S3 +} + +/// V73 Section 2.1: +/// > thirty-two 32-bit general-purpose registers (named R0 through R31) +/// +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +struct GPR(u8); + +impl GPR { + const SP: GPR = GPR(29); + const FP: GPR = GPR(30); + const LR: GPR = GPR(31); +} + +impl fmt::Display for GPR { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + const NAMES: [&'static str; 32] = [ + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", + "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", + "R24", "R25", "R26", "R27", + // the three R29 through R31 general registers support subroutines and the Software + // Stack. ... they have symbol aliases that indicate when these registers are accessed + // as subroutine and stack registers (V73 Section 2.1) + "R28", "SP", "FP", "LR", + ]; + + f.write_str(NAMES[self.0 as usize]) + } +} + +/// V73 Section 2.1: +/// > the general registers can be specified as a pair that represent a single 64-bit register. +/// > +/// > NOTE: the first register in a register pair must always be odd-numbered, and the second must be +/// > the next lower register. +/// +/// from Table 2-2, note there is an entry of `R31:R30 (LR:FP)` +struct RegPair(u8); + +/// V73 Section 2.2: +/// > the Hexagon processor includes a set of 32-bit control registers that provide access to +/// > processor features such as the program counter, hardware loops, and vector predicates. +/// > +/// > unlike general registers, control registers are used as instruction operands only in the +/// > following cases: +/// > * instructions that require a specific control register as an operand +/// > * register transfer instructions +/// > +/// > NOTE: when a control register is used in a register transfer, the other operand must be a +/// > general register. +/// also V73 Section 2.2: +/// > the control registers have numeric aliases (C0 through C31). +/// +/// while the names are written out first, the numeric form of the register is probably what is +/// used more often... +/// +/// also, the `*LO/*HI` registers seem like they may be used in some circumstances as a pair +/// without the `LO/HI` suffixes, so there may need to be a `ControlRegPair` type too. +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +struct ControlReg(u8); + +impl ControlReg { + /// Loop start address register 0 + const SA0: ControlReg = ControlReg(0); + /// Loop count register 0 + const LC0: ControlReg = ControlReg(1); + /// Loop start address register 1 + const SA1: ControlReg = ControlReg(2); + /// Loop count register 1 + const LC1: ControlReg = ControlReg(3); + /// Predicate registers + const PREDICATES: ControlReg = ControlReg(4); + + // C5 is unused + + /// Modifier register 0 + const M0: ControlReg = ControlReg(6); + /// Modifier register 1 + const M1: ControlReg = ControlReg(7); + /// User status register + /// + /// V73 Section 2.2.3: + /// > USR stores the following status and control values: + /// > * Cache prefetch enable + /// > * Cache prefetch status + /// > * Floating point modes + /// > * Floating point status + /// > * Hardware loop configuration + /// > * Sticky Saturation overflow + /// > + /// > NOTE: A user control register transfer to USR cannot be gruoped in an instruction packet + /// with a Floating point instruction. + /// > NOTE: When a transfer to USR chagnes the enable trap bits [29:25], an isync instruction + /// (Section 5.11) must execute before the new exception programming can take effect. + const USR: ControlReg = ControlReg(8); + /// Program counter + const PC: ControlReg = ControlReg(9); + /// User general pointer + const UGP: ControlReg = ControlReg(10); + /// Global pointer + const GP: ControlReg = ControlReg(11); + /// Circular start register 0 + const CS0: ControlReg = ControlReg(12); + /// Circular start register 1 + const CS1: ControlReg = ControlReg(13); + /// Cycle count registers + /// + /// according to V5x manual section 1.5, new in V5x + const UPCYCLELO: ControlReg = ControlReg(14); + /// Cycle count registers + /// + /// according to V5x manual section 1.5, new in V5x + const UPCYCLEHI: ControlReg = ControlReg(15); + /// Stack bounds register + /// + /// V73 Section 2.2.10: + /// > The frame limit register (FRAMELIMIT) stores the low address of the memory area reserved + /// > for the software stack (Section 7.3.1). + const FRAMELIMIT: ControlReg = ControlReg(16); + /// Stack smash register + /// + /// V73 Section 2.2.11: + /// > The frame key register (FRAMEKEY) stores the key value that XOR-scrambles return + /// > addresses when they are stored on the software tack (Section 7.3.2). + const FRAMEKEY: ControlReg = ControlReg(17); + /// Packet count registers + /// + /// v73 Section 2.2.12: + /// > The packet count registers (PKTCOUNTLO to PKTCOUNTHI) store a 64-bit value containing the + /// > current number of instruction packets exceuted since a PKTCOUNT registers was last + /// > written to. + const PKTCOUNTLO: ControlReg = ControlReg(18); + /// Packet count registers + const PKTCOUNTHI: ControlReg = ControlReg(19); + + // C20-C29 are reserved + + /// Qtimer registers + /// + /// V73 Section 2.2.13: + /// > The QTimer registers (UTIMERLO to UTIMERHI) provide access to the QTimer global reference + /// > count value. They enable Hexagon software to read the 64-bit time value without having to + /// > perform an expensive advanced high-performance bus (AHB) load. + /// > ... + /// > These registers are read only – hardware automatically updates these registers to contain + /// > the current QTimer value. + const UTIMERLO: ControlReg = ControlReg(30); + /// Qtimer registers + const UTIMERHI: ControlReg = ControlReg(31); +} + +impl PartialEq for Instruction { + fn eq(&self, other: &Self) -> bool { + panic!("partialeq") + } +} + +impl Instruction { +} + +impl Default for Instruction { + fn default() -> Instruction { + Instruction { + opcode: Opcode::BUG, + dest: None, + predicate: None, + sources: [Operand::Nothing, Operand::Nothing, Operand::Nothing], + sources_count: 0, + } + } +} + +impl fmt::Display for Instruction { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + if let Some(predication) = self.predicate { + write!(f, "if ({}P{}{}) ", + if predication.negated() { "!" } else { "" }, + if predication.pred_new() { ".new" } else { "" }, + predication.num() + )?; + } + + // V73 Section 10.11 + // > The assembler encodes some Hexagon processor instructions as variants of other + // > instructions. The encoding as a variant done for Operations that are functionally + // > equivalent to other instructions, but are still defined as separate instructions because + // > of their programming utility as common operations. + // ... + // | Instruction | Mapping | + // |--------------|------------------| + // | Rd = not(Rs) | Rd = sub(#-1,Rs) | + // | Rd = neg(Rs) | Rd = sub(#0,Rs) | + // | Rdd = Rss | Rdd = combine(Rss.H32, Rss.L32) | + if let Some(o) = self.dest.as_ref() { + write!(f, "{} = ", o)?; + } + write!(f, "{}", self.opcode)?; + if self.sources_count > 0 { + f.write_str("(")?; + write!(f, "{}", self.sources[0])?; + for i in 1..self.sources_count { + write!(f, ", {}", self.sources[i as usize])?; + } + f.write_str(")")?; + } + + Ok(()) + } +} + +impl LengthedInstruction for InstructionPacket { + type Unit = AddressDiff<<Hexagon as Arch>::Address>; + fn min_size() -> Self::Unit { + AddressDiff::from_const(4) + } + fn len(&self) -> Self::Unit { + AddressDiff::from_const(self.word_count as u32 * 4) + } +} + +impl yaxpeax_arch::Instruction for InstructionPacket { + // only know how to decode well-formed instructions at the moment + fn well_defined(&self) -> bool { true } +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum Operand { + Nothing, + /* + /// one of the 16 32-bit general purpose registers: `R0 (sp)` through `R15`. + Register { num: u8 }, + /// one of the 16 32-bit general purpose registers, but a smaller part of it. typically + /// sign-extended to 32b for processing. + Subreg { num: u8, width: SizeCode }, + */ + + PCRel32 { rel: i32 }, + + Gpr { reg: u8 }, + + RegOffset { base: u8, offset: u32, }, + + RegShiftedReg { base: u8, index: u8, shift: u8 }, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum SizeCode { + S, + B, + W, + A, + L, + D, + UW, +} + +impl fmt::Display for SizeCode { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + let text = match self { + SizeCode::S => "s", + SizeCode::B => "b", + SizeCode::W => "w", + SizeCode::A => "a", + SizeCode::L => "l", + SizeCode::D => "d", + SizeCode::UW => "uw", + }; + + f.write_str(text) + } +} + +impl SizeCode { + fn bytes(&self) -> u8 { + match self { + SizeCode::S => 1, + SizeCode::B => 1, + SizeCode::W => 2, + SizeCode::UW => 2, + SizeCode::A => 3, + SizeCode::L => 4, + SizeCode::D => 8, + } + } +} + +/* +impl fmt::Display for Operand { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + } +} +*/ + +impl fmt::Display for Opcode { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + panic!("TODO:"); + } +} + +#[derive(Debug)] +pub struct InstDecoder { } + +impl Default for InstDecoder { + fn default() -> Self { + InstDecoder {} + } +} + +trait DecodeHandler<T: Reader<<Hexagon as Arch>::Address, <Hexagon as Arch>::Word>> { + #[inline(always)] + fn read_u8(&mut self, words: &mut T) -> Result<u8, <Hexagon as Arch>::DecodeError> { + let b = words.next()?; + self.on_word_read(b); + Ok(b) + } + #[inline(always)] + fn read_u16(&mut self, words: &mut T) -> Result<u16, <Hexagon as Arch>::DecodeError> { + let mut buf = [0u8; 2]; + words.next_n(&mut buf).ok().ok_or(DecodeError::ExhaustedInput)?; + self.on_word_read(buf[0]); + self.on_word_read(buf[1]); + Ok(u16::from_le_bytes(buf)) + } + #[inline(always)] + fn read_u32(&mut self, words: &mut T) -> Result<u32, <Hexagon as Arch>::DecodeError> { + let mut buf = [0u8; 4]; + words.next_n(&mut buf).ok().ok_or(DecodeError::ExhaustedInput)?; + self.on_word_read(buf[0]); + self.on_word_read(buf[1]); + self.on_word_read(buf[2]); + self.on_word_read(buf[3]); + Ok(u32::from_le_bytes(buf)) + } + #[inline(always)] + fn read_inst_word(&mut self, words: &mut T) -> Result<u32, <Hexagon as Arch>::DecodeError>; + fn on_decode_start(&mut self) {} + fn on_decode_end(&mut self) {} + fn start_instruction(&mut self); + fn end_instruction(&mut self); + fn on_loop_end(&mut self, loop_num: u8); + fn on_opcode_decoded(&mut self, _opcode: Opcode) -> Result<(), <Hexagon as Arch>::DecodeError> { Ok(()) } + fn on_source_decoded(&mut self, _operand: Operand) -> Result<(), <Hexagon as Arch>::DecodeError> { Ok(()) } + fn on_dest_decoded(&mut self, _operand: Operand) -> Result<(), <Hexagon as Arch>::DecodeError> { Ok(()) } + fn inst_predicated(&mut self, num: u8, negated: bool, pred_new: bool) -> Result<(), <Hexagon as Arch>::DecodeError> { Ok(()) } + fn on_word_read(&mut self, _word: <Hexagon as Arch>::Word) {} +} + +impl<T: yaxpeax_arch::Reader<<Hexagon as Arch>::Address, <Hexagon as Arch>::Word>> DecodeHandler<T> for InstructionPacket { + fn on_decode_start(&mut self) { + self.instructions = [Instruction::default(); 4]; + self.instruction_count = 0; + self.word_count = 0; + } + fn on_loop_end(&mut self, loop_num: u8) { + self.loop_effect.mark_end(loop_num); + } + fn on_opcode_decoded(&mut self, opcode: Opcode) -> Result<(), <Hexagon as Arch>::DecodeError> { + self.instructions[self.instruction_count as usize].opcode = opcode; + Ok(()) + } + fn on_source_decoded(&mut self, operand: Operand) -> Result<(), <Hexagon as Arch>::DecodeError> { + let mut inst = &mut self.instructions[self.instruction_count as usize]; + inst.sources[inst.sources_count as usize] = operand; + inst.sources_count += 1; + Ok(()) + } + fn on_dest_decoded(&mut self, operand: Operand) -> Result<(), <Hexagon as Arch>::DecodeError> { + let mut inst = &mut self.instructions[self.instruction_count as usize]; + assert!(inst.dest.is_none()); + inst.dest = Some(operand); + Ok(()) + } + fn inst_predicated(&mut self, num: u8, negated: bool, pred_new: bool) -> Result<(), <Hexagon as Arch>::DecodeError> { + let mut inst = &mut self.instructions[self.instruction_count as usize]; + assert!(inst.predicate.is_none()); + inst.predicate = Some(Predicate::reg(num).set_negated().set_pred_new()); + Ok(()) + } + #[inline(always)] + fn read_inst_word(&mut self, words: &mut T) -> Result<u32, <Hexagon as Arch>::DecodeError> { + self.word_count += 1; + self.read_u32(words) + } + fn on_word_read(&mut self, _word: <Hexagon as Arch>::Word) { } + fn start_instruction(&mut self) { } + fn end_instruction(&mut self) { + self.instruction_count += 1; + } +} + +impl Decoder<Hexagon> for InstDecoder { + fn decode_into<T: Reader<<Hexagon as Arch>::Address, <Hexagon as Arch>::Word>>(&self, packet: &mut InstructionPacket, words: &mut T) -> Result<(), <Hexagon as Arch>::DecodeError> { + decode_packet(self, packet, words) + } +} + +fn reg_b0(inst: u32) -> u8 { (inst & 0b11111) as u8 } +fn reg_b8(inst: u32) -> u8 { ((inst >> 8) & 0b11111) as u8 } +fn reg_b16(inst: u32) -> u8 { ((inst >> 16) & 0b11111) as u8 } + +fn decode_packet< + T: Reader<<Hexagon as Arch>::Address, <Hexagon as Arch>::Word>, + H: DecodeHandler<T>, +>(decoder: &<Hexagon as Arch>::Decoder, handler: &mut H, words: &mut T) -> Result<(), <Hexagon as Arch>::DecodeError> { + handler.on_decode_start(); + + let mut current_word = 0; + + // V73 Section 10.6: + // > In addition to encoding the last instruction in a packet, the Parse field of the + // > instruction word (Section 10.5) encodes the last packet in a hardware loop. + // + // accumulate Parse fields to comapre against V73 Table 10-7 once we've read the whole + // packet. + // + // TODO: if the first instruction is a duplex, does that mean the packet cannot indicate + // loop end? + let mut loop_bits: u8 = 0b0000; + + // V74 Section 10.6: + // > A constant extender is encoded as a 32-bit instruction with the 4-bit ICLASS field set to + // > 0 and the 2-bit Parse field set to its usual value (Section 10.5). The remaining 26 bits in + // > the instruction word store the data bits that are prepended to an operand as small as six + // > bits to create a full 32-bit value. + // > ... + // > If the instruction operand to extend is longer than six bits, the overlapping bits in the + // > base instruction must be encoded as zeros. The value in the constant extender always + // > supplies the upper 26 bits. + let mut extender: Option<u32> = None; + + // have we seen an end of packet? + let mut end = false; + + while !end { + if current_word >= 4 { + panic!("TODO: instruction too large"); + // Err(DecodeError::InstructionTooLarge) + } + + let inst: u32 = handler.read_inst_word(words)?; + + println!("read word {:08x}", inst); + + // V73 Section 10.5: + // > Instruction packets are encoded using two bits of the instruction word (15:14), whic + // > are referred to as the Parse field of the instruction word. + let parse = (inst >> 14) & 0b11; + + if current_word == 0 { + loop_bits |= parse as u8; + } else if current_word == 1 { + loop_bits |= (parse as u8) << 2; + } + + // V73 Section 10.5: + // > 11 indicates that an instruction is the last instruction in a packet + // > 01 or 10 indicate that an instruction is not the last instruction in a packet + // > 00 indicates a duplex + match parse { + 0b00 => { + println!("duplex,"); + } + 0b01 | 0b10 => { + println!("middle"); + } + 0b11 => { + println!("eop"); + end = true; + + if loop_bits & 0b0111 == 0b0110 { + handler.on_loop_end(0); + } else if loop_bits == 0b1001 { + handler.on_loop_end(1); + } else if loop_bits == 0b1010 { + handler.on_loop_end(0); + handler.on_loop_end(1); + } + } + _ => { + unreachable!(); + } + } + + let iclass = (inst >> 28) & 0b1111; + println!(" iclass: {:04b}", iclass); + + + if iclass == 0b0000 { + extender = Some((inst & 0x3fff) | ((inst >> 2) & 0xfff)); + } else { + handler.start_instruction(); + decode_instruction(decoder, handler, inst, extender)?; + handler.end_instruction(); + } + + current_word += 1; + } + + Ok(()) +} + +fn can_be_extended(iclass: u8, regclass: u8) -> bool { + panic!("TODO: Table 10-10") +} + +fn decode_instruction< + T: Reader<<Hexagon as Arch>::Address, <Hexagon as Arch>::Word>, + H: DecodeHandler<T>, +>(decoder: &<Hexagon as Arch>::Decoder, handler: &mut H, inst: u32, extender: Option<u32>) -> Result<(), <Hexagon as Arch>::DecodeError> { + let iclass = (inst >> 28) & 0b1111; + + // V73 Section 10.9 + // > A constant extender must be positioned in a packet immediately before the + // > instruction that it extends + // > ... + // > If a constant extender is encoded in a packet for an instruction that does not + // > accept a constant extender, the execution result is undefined. The assembler + // > normally ensures that only valid constant extenders are generated. + if extender.is_some() { + eprintln!("TODO: error; unconsumed extender"); + } + + // this is *called* "RegType" in the manual but it seem to more often describe + // opcodes? + let reg_type = (inst >> 24) & 0b1111; + let min_op = (inst >> 21) & 0b111; + + match iclass { + 0b0011 => { + let upper = (inst >> 26) & 0b11; + match upper { + 0b00 => { + // 00011 | 00xxxxxxx + // everything under this is a predicated load + let nn = (inst >> 24) & 0b11; + + let negated = nn & 1 == 1; + let pred_new = nn >> 1 == 1; + + let ddddd = reg_b0(inst); + let vv = ((inst >> 5) & 0b11) as u8; + let i_lo = (inst >> 7) & 0b1; + let ttttt = reg_b8(inst); + let i_hi = ((inst >> 13) & 0b1) << 1; + let ii = (i_lo | i_hi) as u8; + let sssss = reg_b16(inst); + let op = (inst >> 21) & 0b111; + + handler.inst_predicated(vv, negated, pred_new); + handler.on_source_decoded(Operand::RegShiftedReg { base: sssss, index: ttttt, shift: ii })?; + handler.on_dest_decoded(Operand::Gpr { reg: ddddd })?; + + use Opcode::*; + static OPCODES: [Option<Opcode>; 8] = [ + Some(Memb), Some(Memub), Some(Memh), Some(Memuh), + Some(Memw), None, Some(Memd), None, + ]; + handler.on_opcode_decoded(OPCODES[op as usize].ok_or(DecodeError::InvalidOpcode)?); + } + other => { + panic!("TODO: other: {}", other); + } + } + } + 0b0101 => { + let majop = (inst >> 25) & 0b111; + match majop { + 0b100 => { + // V73 Jump to address + // 0 1 0 1 | 1 0 0 i... + handler.on_opcode_decoded(Opcode::Jump); + let imm = ((inst >> 1) & 0x7fff) | ((inst >> 3) & 0xff8000); + let imm = ((imm as i32) << 10) >> 10; + handler.on_source_decoded(Operand::PCRel32 { rel: imm & !0b11 })?; + }, + _ => { + // TODO: exhaustive + } + } + }, + 0b0111 => { + if reg_type == 0b0000 { + static OPS: [Option<Opcode>; 8] = [ + Some(Opcode::Aslh), Some(Opcode::Asrh), None, Some(Opcode::Mov), + Some(Opcode::Zxtb), Some(Opcode::Sxtb), Some(Opcode::Zxth), Some(Opcode::Sxth), + ]; + + let Some(opcode) = OPS[min_op as usize] else { + return Err(DecodeError::InvalidOpcode); + }; + + let ddddd = reg_b0(inst); + let sssss = reg_b16(inst); + let predicated = (inst >> 15) & 1 != 0; + + if opcode == Opcode::Mov && predicated { + // no support for predicated register transfer..? + return Err(DecodeError::InvalidOpcode); + } else if opcode == Opcode::Zxtb && !predicated { + // non-predicated zext is assembled as `Rd=and(Rs,#255)` + // really curious if hardware supports this instruction anyway... + return Err(DecodeError::InvalidOpcode); + } + + handler.on_opcode_decoded(opcode); + + if predicated { + let pred_bits = (inst >> 10) & 0b11; + let negated = pred_bits >> 1 != 0; + let dotnew = pred_bits & 1 != 0; + let pred_number = (inst >> 8) & 0b11; + + handler.inst_predicated(pred_number as u8, negated, dotnew); + } + + handler.on_dest_decoded(Operand::Gpr { reg: ddddd })?; + handler.on_source_decoded(Operand::Gpr { reg: sssss })?; + } else { + } + if (inst >> 24) & 0b1111 == 0b1111 { + handler.on_opcode_decoded(Opcode::Nop); + } + } + 0b1001 => { + if (inst >> 27) & 1 != 0 { + panic!("other mem op"); + } + + let ddddd = reg_b0(inst); + let sssss = reg_b16(inst); + let i_lo = (inst >> 5) & 0b1_1111_1111; + let i_hi = (inst >> 25) & 0b11; + let i = i_lo | (i_hi << 9); + let op = (inst >> 21) & 0b1111; + + static SAMT: [u8; 16] = [ + 0xff, 0x01, 0x00, 0x01, + 0x00, 0x02, 0xff, 0x02, + 0x03, 0x03, 0x03, 0x03, + 0x03, 0xff, 0x03, 0xff, + ]; + + handler.on_source_decoded(Operand::RegOffset { base: sssss, offset: (i as u32) << SAMT[op as usize] }); + handler.on_dest_decoded(Operand::Gpr { reg: ddddd })?; + + use Opcode::*; + static OPCODES: [Option<Opcode>; 16] = [ + None, Some(Membh), Some(MemhFifo), Some(Memubh), + Some(MembFifo), Some(Memubh), None, Some(Membh), + Some(Memb), Some(Memub), Some(Memh), Some(Memuh), + Some(Memw), None, Some(Memd), None, + ]; + handler.on_opcode_decoded(OPCODES[op as usize].ok_or(DecodeError::InvalidOpcode)?); + } + _ => { + // TODO: exhaustive + } + } + + Ok(()) +} |