yaxpeax-hexagon - yaxpeax hexagon decoder

Age	Commit message (Collapse)	Author
5 days	actually commit the fuzz target and a bit of test binary	iximeow

5 days	another fuzz victory!	iximeow

5 days	fuzz cases: only 64 system registers, display should never panic	iximeow

5 days	seeming good	iximeow

5 days	l2 cache management instructions are system and undocumented	iximeow

6 days	shift plus extenders no longer ambiguous	iximeow

6 days	the rest of the extenders	iximeow

6 days	predicated store was RegOffset when it should be RegOffsetInc	iximeow
	and a few more extender tests
6 days	just... decoded predicated loads wrong...	iximeow

6 days	more instruction extenders	iximeow

6 days	initial list of extendable instructions, fix memub/memuh decode errors	iximeow

6 days	initial instruction extender support, more system instructions	iximeow

7 days	more registers as lower case, pc-relative shown like every other arch	iximeow

9 days	llvm accepts lowercase register names so LETS GOOOOO	iximeow

9 days	control, gpr register names, readme	iximeow

10 days	system control register names, more cleanup	iximeow

10 days	supervisor mode instructions, control register names	iximeow

11 days	wowowowow cargo test passes	iximeow

12 days	it is done (not all system, duplex, extender tho)	iximeow

12 days	sfrecipa, more test cases, more inst variants	iximeow

12 days	more test coverage, getting close..	iximeow

12 days	more tests and cleanup; sub, instruction labels, sfmpy	iximeow
	additionally, AndNot should show its special assign mode if one is set. a few instructions have 64-bit register pairs that can be conjugated. vrmpywoh should have operands. :sat applied incompletely AndNot can have \|=, &=, and ^= assign modes, not += had a sub with backwards operands
12 days	wretched architecture which does not know the light of g*d	iximeow

12 days	more pmpy, ignore shift_{left,right} with amt=0	iximeow

12 days	gross hacks for AddAsl, fix AddMpyi decoding	iximeow

12 days	more test coverage, gpr conjugates	iximeow

12 days	shift vs sat order in display, vxaddsubh/vxsubaddh/extractu/decbin	iximeow

12 days	fix extractu/shuff{e,o}{b,h}, add many test cases, handle AddMpyi	iximeow

13 days	theoretically all non-system instructions...	iximeow

2025-03-29	1101* is all thats left...	iximeow

2025-03-28	0b1000..0b1100: DONE!	iximeow

2025-03-23	shifts and MORE transcription errors :(	iximeow

2025-03-23	thats 0110... done	iximeow

2025-03-23	more loop support, transcription errors, etc	iximeow

2025-03-22	wow 1001... is done now	iximeow

2025-03-22	more loads, fix wrong dest ops for some loads..	iximeow

2025-03-22	more tests, support more loads/stores	iximeow

2025-03-21	assign-merge is recorded now, 0100.. is decoded	iximeow

2025-03-19	moderate progress...	iximeow

2024-12-23	checkpoint	iximeow

2024-11-10	some iclass 1100, 1010, 1001	iximeow

2024-10-08	more progress	iximeow

2024-10-06	more support, docs about some weird instruction shapes	iximeow

2024-10-05	more ops, transcription errors	iximeow

2024-10-05	broader support, maybe 1/8th through. also v73 manual does not list ↵	iximeow
	supervisor instructions...
2024-09-29	starting to look like a disassembler	iximeow