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2 daysactually commit the fuzz target and a bit of test binaryiximeow
2 daysanother fuzz victory!iximeow
2 daysfuzz cases: only 64 system registers, display should never paniciximeow
2 daysseeming goodiximeow
2 daysl2 cache management instructions are system and undocumentediximeow
3 daysshift plus extenders no longer ambiguousiximeow
3 daysthe rest of the extendersiximeow
3 dayspredicated store was RegOffset when it should be RegOffsetInciximeow
3 daysjust... decoded predicated loads wrong...iximeow
3 daysmore instruction extendersiximeow
3 daysinitial list of extendable instructions, fix memub/memuh decode errorsiximeow
4 daysinitial instruction extender support, more system instructionsiximeow
4 daysmore registers as lower case, pc-relative shown like every other archiximeow
6 daysllvm accepts lowercase register names so LETS GOOOOOiximeow
6 dayscontrol, gpr register names, readmeiximeow
7 dayssystem control register names, more cleanupiximeow
7 dayssupervisor mode instructions, control register namesiximeow
8 dayswowowowow cargo test passesiximeow
9 daysit is done (not all system, duplex, extender tho)iximeow
9 dayssfrecipa, more test cases, more inst variantsiximeow
9 daysmore test coverage, getting close..iximeow
9 daysmore tests and cleanup; sub, instruction labels, sfmpyiximeow
9 dayswretched architecture which does not know the light of g*diximeow
9 daysmore pmpy, ignore shift_{left,right} with amt=0iximeow
10 daysgross hacks for AddAsl, fix AddMpyi decodingiximeow
10 daysmore test coverage, gpr conjugatesiximeow
10 daysshift vs sat order in display, vxaddsubh/vxsubaddh/extractu/decbiniximeow
10 daysfix extractu/shuff{e,o}{b,h}, add many test cases, handle AddMpyiiximeow
10 daystheoretically all non-system instructions...iximeow
2025-03-291101* is all thats left...iximeow
2025-03-280b1000..0b1100: DONE!iximeow
2025-03-23shifts and MORE transcription errors :(iximeow
2025-03-23thats 0110... doneiximeow
2025-03-23more loop support, transcription errors, etciximeow
2025-03-22wow 1001... is done nowiximeow
2025-03-22more loads, fix wrong dest ops for some loads..iximeow
2025-03-22more tests, support more loads/storesiximeow
2025-03-21assign-merge is recorded now, 0100.. is decodediximeow
2025-03-19moderate progress...iximeow
2024-12-23checkpointiximeow
2024-11-10some iclass 1100, 1010, 1001iximeow
2024-10-08more progressiximeow
2024-10-06more support, docs about some weird instruction shapesiximeow
2024-10-05more ops, transcription errorsiximeow
2024-10-05broader support, maybe 1/8th through. also v73 manual does not list superviso...iximeow
2024-09-29starting to look like a disassembleriximeow