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|0 0 0 1 0 0| VD128 | RA | RB |0 0 0 0 0 0 0|VDh|1 1| lvsl128 Load Vector128 for Shift Left
|0 0 0 1 0 0| VD128 | RA | RB |0 0 0 0 1 0 0|VDh|1 1| lvsr128 Load Vector128 for Shift Right
|0 0 0 1 0 0| VD128 | RA | RB |0 0 0 1 0 0 0|VDh|1 1| lvewx128 Load Vector128 Element Word Indexed
|0 0 0 1 0 0| VD128 | RA | RB |0 0 0 1 1 0 0|VDh|1 1| lvx128 Load Vector128 Indexed
|0 0 0 1 0 0| VS128 | RA | RB |0 0 1 1 0 0 0|VDh|1 1| stvewx128 Store Vector128 Element Word Indexed
|0 0 0 1 0 0| VS128 | RA | RB |0 0 1 1 1 0 0|VDh|1 1| stvx128 Store Vector128 Indexed
|0 0 0 1 0 0| VD128 | RA | RB |0 1 0 1 1 0 0|VDh|1 1| lvxl128 Load Vector128 Indexed LRU
|0 0 0 1 0 0| VS128 | RA | RB |0 1 1 1 1 0 0|VDh|1 1| stvxl128 Store Vector128 Indexed LRU
|0 0 0 1 0 0| VD128 | RA | RB |1 0 0 0 0 0 0|VDh|1 1| lvlx128 Load Vector128 Left Indexed
|0 0 0 1 0 0| VD128 | RA | RB |1 0 0 0 1 0 0|VDh|1 1| lvrx128 Load Vector128 Right Indexed
|0 0 0 1 0 0| VS128 | RA | RB |1 0 1 0 0 0 0|VDh|1 1| stvlx128 Store Vector128 Left Indexed
|0 0 0 1 0 0| VS128 | RA | RB |1 0 1 0 1 0 0|VDh|1 1| stvrx128 Store Vector128 Right Indexed
|0 0 0 1 0 0| VD128 | RA | RB |1 1 0 0 0 0 0|VDh|1 1| lvlxl128 Load Vector128 Left Indexed LRU
|0 0 0 1 0 0| VD128 | RA | RB |1 1 0 0 1 0 0|VDh|1 1| lvrxl128 Load Vector128 Right Indexed LRU
|0 0 0 1 0 0| VS128 | RA | RB |1 1 1 0 0 0 0|VDh|1 1| stvlxl128 Store Vector128 Left Indexed LRU
|0 0 0 1 0 0| VS128 | RA | RB |1 1 1 0 1 0 0|VDh|1 1| stvrxl128 Store Vector128 Right Indexed LRU
|0 0 0 1 0 0| VD128 | VA128 | VB128 |A| SHB |a|1|VDh|VBh| vsldoi128 Vector128 Shift Left Double by Octet Immediate
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0| VC |a|0|VDh|VBh| vperm128 Vector128 Permutation
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 0|a|0|VDh|VBh| vpkshss128 Vector128 Pack Signed Half Word Signed Saturate
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 1|a|0|VDh|VBh| vpkshus128 Vector128 Pack Signed Half Word Unsigned Saturate
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 0|a|0|VDh|VBh| vpkswss128 Vector128 Pack Signed Word Signed Saturate
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 1|a|0|VDh|VBh| vpkswus128 Vector128 Pack Signed Word Unsigned Saturate
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 0 0|a|0|VDh|VBh| vpkuhum128 Vector128 Pack Unsigned Half Word Unsigned Modulo
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 0 1|a|0|VDh|VBh| vpkuhus128 Vector128 Pack Unsigned Half Word Unsigned Saturate
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 0|a|0|VDh|VBh| vpkuwum128 Vector128 Pack Unsigned Word Unsigned Modulo
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 1|a|0|VDh|VBh| vpkuwus128 Vector128 Pack Unsigned Word Unsigned Saturate
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 0 0|a|1|VDh|VBh| vaddfp128 Vector128 Add Floating Point
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 0 1|a|1|VDh|VBh| vsubfp128 Vector128 Subtract Floating Point
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 1 0|a|1|VDh|VBh| vmulfp128 Vector128 Multiply Floating-Point
|0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|0 0 1 1|a|1|VDh|VBh| vmaddfp128 Vector128 Multiply Add Floating Point
|0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|0 1 0 0|a|1|VDh|VBh| vmaddcfp128 Vector128 Multiply Add Floating Point
|0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|0 1 0 1|a|1|VDh|VBh| vnmsubfp128 Vector128 Negative Multiply-Subtract Floating Point
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 1 1 0|a|1|VDh|VBh| vmsum3fp128 Vector128 Multiply Sum 3-way Floating Point
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 1 1 1|a|1|VDh|VBh| vmsum4fp128 Vector128 Multiply Sum 4-way Floating-Point
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 0|a|1|VDh|VBh| vand128 Vector128 Logical AND
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 1|a|1|VDh|VBh| vandc128 Vector128 Logical AND with Complement
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 0|a|1|VDh|VBh| vnor128 Vector128 Logical NOR
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 1|a|1|VDh|VBh| vor128 Vector128 Logical OR
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 0 0|a|1|VDh|VBh| vxor128 Vector128 Logical XOR <--- vxor128 missing!!
|0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|1 1 0 1|a|1|VDh|VBh| vsel128 Vector128 Select
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 0|a|1|VDh|VBh| vslo128 Vector128 Shift Left Octet
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 1|a|1|VDh|VBh| vsro128 Vector128 Shift Right Octet
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 0 0|R|a|0|VDh|VBh| vcmpeqfp128 Vector128 Compare Equal-to Floating Point
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 0 1|R|a|0|VDh|VBh| vcmpgefp128 Vector128 Compare Greater-Than- or-Equal-to Floating Point
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 0|R|a|0|VDh|VBh| vcmpgtfp128 Vector128 Compare Greater-Than Floating-Point
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 1|R|a|0|VDh|VBh| vcmpbfp128 Vector128 Compare Bounds Floating Point
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 0 0|R|a|0|VDh|VBh| vcmpequw128 Vector128 Compare Equal-to Unsigned Word
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 0 1 0|a|0|VDh|VBh| vmaxfp128 Vector128 Maximum Floating Point
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 0 1 1|a|0|VDh|VBh| vminfp128 Vector128 Minimum Floating Point
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 1 0 0|a|0|VDh|VBh| vmrghw128 Vector128 Merge High Word
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 1 0 1|a|0|VDh|VBh| vmrglw128 Vector128 Merge Low Word
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 0 0 0|VDh|VBh| vupkhsb128 Vector128 Unpack High Signed Byte
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 1 0 0|VDh|VBh| vupklsb128 Vector128 Unpack Low Signed Byte
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 0 1|a|1|VDh|VBh| vrlw128 Vector128 Rotate Left Word <--- is this wrong, should be opc 6?
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 0 1 1|a|1|VDh|VBh| vslw128 Vector128 Shift Left Word
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 0 1|a|1|VDh|VBh| vsraw128 Vector128 Shift Right Arithmetic Word
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 1 1|a|1|VDh|VBh| vsrw128 Vector128 Shift Right Word
|0 0 0 1 1 0| VD128 | PERMl | VB128 |0|1|PERMh|0|1|VDh|VBh| vpermwi128 Vector128 Permutate Word Immediate
|0 0 0 1 1 0| VD128 | SIMM | VB128 |0 1 0 0 0 1 1|VDh|VBh| vcfpsxws128 Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate
|0 0 0 1 1 0| VD128 | UIMM | VB128 |0 1 0 0 1 1 1|VDh|VBh| vcfpuxws128 Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate
|0 0 0 1 1 0| VD128 | UIMM | VB128 |0 1 0 1 0 1 1|VDh|VBh| vcsxwfp128 Vector128 Convert From Signed Fixed-Point Word to Floating-Point
|0 0 0 1 1 0| VD128 | UIMM | VB128 |0 1 0 1 1 1 1|VDh|VBh| vcuxwfp128 Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 0 0 1 1|VDh|VBh| vrfim128 Vector128 Round to Floating-Point Integer toward -oo
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 0 1 1 1|VDh|VBh| vrfin128 Vector128 Round to Floating-Point Integer toward Nearest
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 0 1 1|VDh|VBh| vrfip128 Vector128 Round to Floating-Point Integer toward +oo
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 1 1 1|VDh|VBh| vrfiz128 Vector128 Round to Floating-Point Integer toward Zero
|0 0 0 1 1 0| VD128 | x | y | VB128 |1 1 0| z |0 1|VDh|VBh| vpkd3d128 Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert
|0 0 0 1 1 0| VD128 | UIMM | VB128 |1 1 1| z |0 1|VDh|VBh| vrlimi128 Vector128 Rotate Left Immediate and Mask Insert
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 0 0 1 1|VDh|VBh| vrefp128 Vector128 Reciprocal Estimate Floating Point
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 0 1 1 1|VDh|VBh| vrsqrtefp128 Vector128 Reciprocal Square Root Estimate Floating Point
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 1 0 1 1|VDh|VBh| vexptefp128 Vector128 2 Raised to the Exponent Estimate Floating Point
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 1 1 1 1|VDh|VBh| vlogefp128 Vector128 Log2 Estimate Floating Point
|0 0 0 1 1 0| VD128 | UIMM | VB128 |1 1 1 0 0 1 1|VDh|VBh| vspltw128 Vector128 Splat Word
|0 0 0 1 1 0| VD128 | SIMM | VB128 |1 1 1 0 1 1 1|VDh|VBh| vspltisw128 Vector128 Splat Immediate Signed Word <---- this is two operands, not three
|0 0 0 1 1 0| VD128 | UIMM | VB128 |1 1 1 1 1 1 1|VDh|VBh| vupkd3d128 Vector128 Unpack D3Dtype
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