pextr*/pinsr*/insertps/extrps immediate is now u8 instead of i8

7 files changed, 13 insertions, 9 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 95851c6..a437a4f 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -20,6 +20,10 @@
 * fix incorrect index-vector-register size choice for vgatherdpd. the index register is xmm, not
   depends-on-L xmm/ymm.
 * fix SEAM and {rd,wr}{fs,gs}base instructions being decoded in 32-bit and 16-bit modes.
+* the pextr*/pinsr*/insertps/extrps immediate is now an unsigned 8-bit immediate, rather than signed.
+  these instructions consume 8 bit of immediate as several fields compressed into 8 bits, rather
+  than as a numeric value, so sign extension is not useful.  further, extending the immediate makes
+  it more difficult to round-trip disassembly through other assemblers.
 
 testing instruction round-tripping through `masm` found a few bugs, which are also fixed in this release:
 
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 01b2f08..ad2915c 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -6741,7 +6741,7 @@ fn read_operands<
             } else {
                 instruction.regs[1].bank = RegisterBank::X;
             }
-            instruction.operands[2] = OperandSpec::ImmI8;
+            instruction.operands[2] = OperandSpec::ImmU8;
             instruction.operand_count = 3;
         }
         OperandCase::G_Ev_xmm_Ib => {
@@ -6760,7 +6760,7 @@ fn read_operands<
             } else {
                 instruction.regs[1].bank = RegisterBank::X;
             }
-            instruction.operands[2] = OperandSpec::ImmI8;
+            instruction.operands[2] = OperandSpec::ImmU8;
             instruction.operand_count = 3;
         }
         OperandCase::PMOVX_E_G_xmm => {
diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index 54c9c0a..8bf15a4 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -6600,7 +6600,7 @@ fn read_operands<
             } else {
                 instruction.regs[1].bank = RegisterBank::X;
             }
-            instruction.operands[2] = OperandSpec::ImmI8;
+            instruction.operands[2] = OperandSpec::ImmU8;
             instruction.operand_count = 3;
         }
         OperandCase::G_Ev_xmm_Ib => {
@@ -6619,7 +6619,7 @@ fn read_operands<
             } else {
                 instruction.regs[1].bank = RegisterBank::X;
             }
-            instruction.operands[2] = OperandSpec::ImmI8;
+            instruction.operands[2] = OperandSpec::ImmU8;
             instruction.operand_count = 3;
         }
         OperandCase::PMOVX_E_G_xmm => {
diff --git a/src/real_mode/mod.rs b/src/real_mode/mod.rs
index 6e7aaa4..8d4e4dd 100644
--- a/src/real_mode/mod.rs
+++ b/src/real_mode/mod.rs
@@ -6640,7 +6640,7 @@ fn read_operands<
             } else {
                 instruction.regs[1].bank = RegisterBank::X;
             }
-            instruction.operands[2] = OperandSpec::ImmI8;
+            instruction.operands[2] = OperandSpec::ImmU8;
             instruction.operand_count = 3;
         }
         OperandCase::G_Ev_xmm_Ib => {
@@ -6659,7 +6659,7 @@ fn read_operands<
             } else {
                 instruction.regs[1].bank = RegisterBank::X;
             }
-            instruction.operands[2] = OperandSpec::ImmI8;
+            instruction.operands[2] = OperandSpec::ImmU8;
             instruction.operand_count = 3;
         }
         OperandCase::PMOVX_E_G_xmm => {
diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs
index cd8fbbb..fb38840 100644
--- a/test/long_mode/mod.rs
+++ b/test/long_mode/mod.rs
@@ -4525,7 +4525,7 @@ mod mishegos_finds {
         testcase!(&[0x66, 0x3e, 0x26, 0x2e, 0x2e, 0x0f, 0x38, 0x2a, 0x2b, ], "movntdqa xmm5, xmmword [rbx]"),
         testcase!(&[0x66, 0x2e, 0x67, 0x0f, 0x3a, 0x0d, 0xb8, 0xf0, 0x2f, 0x7c, 0xf0, 0x63, ], "blendpd xmm7, xmmword [eax - 0xf83d010], 0x63"),
         testcase!(&[0x66, 0x66, 0x64, 0x3e, 0x0f, 0x38, 0x23, 0x9d, 0x69, 0x0f, 0xa8, 0x2d, ], "pmovsxwd xmm3, qword fs:[rbp + 0x2da80f69]"),
-        testcase!(&[0x2e, 0x66, 0x26, 0x64, 0x49, 0x0f, 0x3a, 0x21, 0x0b, 0xb1, ], "insertps xmm1, dword fs:[r11], -0x4f"),
+        testcase!(&[0x2e, 0x66, 0x26, 0x64, 0x49, 0x0f, 0x3a, 0x21, 0x0b, 0xb1, ], "insertps xmm1, dword fs:[r11], 0xb1"),
         testcase!(&[0x66, 0x26, 0x45, 0x0f, 0x3a, 0x42, 0x96, 0x74, 0x29, 0x96, 0xf9, 0x6a], "mpsadbw xmm10, xmmword [r14 - 0x669d68c], 0x6a"),
         testcase!(&[0x67, 0x26, 0x66, 0x65, 0x0f, 0x38, 0x3f, 0x9d, 0xcc, 0x03, 0xb3, 0xfa], "pmaxud xmm3, xmmword gs:[ebp - 0x54cfc34]"),
         testcase!(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], "movdiri dword [rbp + 0x3e], edx", masm: "movdiri dword ptr [rbp + 3Eh], edx"),
diff --git a/test/protected_mode/mod.rs b/test/protected_mode/mod.rs
index be16635..6cf4cc5 100644
--- a/test/protected_mode/mod.rs
+++ b/test/protected_mode/mod.rs
@@ -4228,7 +4228,7 @@ mod mishegos_finds {
         testcase!(&[0x66, 0x3e, 0x26, 0x2e, 0x2e, 0x0f, 0x38, 0x2a, 0x2b], "movntdqa xmm5, xmmword cs:[ebx]"),
         testcase!(&[0x66, 0x2e, 0x67, 0x0f, 0x3a, 0x0d, 0xb8, 0xf0, 0x2f, 0x7c], "blendpd xmm7, xmmword cs:[bx + si * 1 + 0x2ff0], 0x7c"),
         testcase!(&[0x66, 0x66, 0x64, 0x3e, 0x0f, 0x38, 0x23, 0x9d, 0x69, 0x0f, 0xa8, 0x2d], "pmovsxwd xmm3, qword [ebp + 0x2da80f69]"),
-        testcase!(&[0x2e, 0x66, 0x26, 0x64, 0x0f, 0x3a, 0x21, 0x0b, 0xb1], "insertps xmm1, dword fs:[ebx], -0x4f"),
+        testcase!(&[0x2e, 0x66, 0x26, 0x64, 0x0f, 0x3a, 0x21, 0x0b, 0xb1], "insertps xmm1, dword fs:[ebx], 0xb1"),
         testcase!(&[0x66, 0x26, 0x0f, 0x3a, 0x42, 0x96, 0x74, 0x29, 0x96, 0xf9, 0x6a], "mpsadbw xmm2, xmmword es:[esi - 0x669d68c], 0x6a"),
         testcase!(&[0x67, 0x26, 0x66, 0x65, 0x0f, 0x38, 0x3f, 0x9d, 0xcc, 0x03], "pmaxud xmm3, xmmword gs:[di + 0x3cc]"),
         testcase!(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e], "movdiri dword cs:[ebp + 0x3e], edx"),
diff --git a/test/real_mode/mod.rs b/test/real_mode/mod.rs
index e7be755..9f6bdf3 100644
--- a/test/real_mode/mod.rs
+++ b/test/real_mode/mod.rs
@@ -779,7 +779,7 @@ mod real_mode {
         testcase!(&[0x2e, 0x36, 0x0f, 0x18, 0xe7], "nop di"),
         testcase!(&[0x2e, 0x3e, 0x66, 0x3e, 0x0f, 0x3a, 0x41, 0x30, 0x48], "dppd xmm6, xmmword [bx + si * 1], 0x48"),
         testcase!(&[0x2e, 0x66, 0x0f, 0x3a, 0x0d, 0x40, 0x2d, 0x57], "blendpd xmm0, xmmword cs:[bx + si * 1 + 0x2d], 0x57"),
-        testcase!(&[0x2e, 0x66, 0x26, 0x64, 0x0f, 0x3a, 0x21, 0x0b, 0xb1], "insertps xmm1, dword fs:[bp + di * 1], -0x4f"),
+        testcase!(&[0x2e, 0x66, 0x26, 0x64, 0x0f, 0x3a, 0x21, 0x0b, 0xb1], "insertps xmm1, dword fs:[bp + di * 1], 0xb1"),
         testcase!(&[0x2f], "das"),
         testcase!(&[0x31, 0xc9], "xor cx, cx"),
         testcase!(&[0x33, 0x04], "xor ax, word [si]"),