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authoriximeow <me@iximeow.net>2020-10-27 00:57:33 -0700
committeriximeow <me@iximeow.net>2020-10-27 00:57:33 -0700
commit39aaebeb48c30b96b4ff8b66663a1452e2571426 (patch)
tree6d87158a84ab9e9865bdb86a2ab27290cdb94436
parentfb9ead64e6c7d96c02627b01b6a85921e2d8f7a4 (diff)
fix misdecode of instructions in opcode 0x800.1.3
-rw-r--r--CHANGELOG4
-rw-r--r--Cargo.toml2
-rw-r--r--src/long_mode/mod.rs1
-rw-r--r--src/protected_mode/mod.rs1
-rw-r--r--test/long_mode/mod.rs1
-rw-r--r--test/protected_mode/mod.rs1
6 files changed, 9 insertions, 1 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 6e811e0..5f0b9f7 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,7 @@
+## 0.1.3
+* fix 0x80-opcode instructions not having an opcode
+ - this meant that for example `lock xorb [rax], 0` would decode as invalid
+
## 0.1.2
* expose constructors for `RegSpec` in both `long_mode` and `protected_mode`
* expose a const `RegSpec::RIP`
diff --git a/Cargo.toml b/Cargo.toml
index 10f0962..c6da196 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,7 +1,7 @@
[package]
name = "yaxpeax-x86"
-version = "0.1.2"
+version = "0.1.3"
authors = [ "iximeow <me@iximeow.net>" ]
license = "0BSD"
repository = "http://git.iximeow.net/yaxpeax-x86/"
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 94e34ae..363c605 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -6171,6 +6171,7 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T,
instruction.operand_count = 1;
},
1 => {
+ instruction.opcode = base_opcode_map((modrm >> 3) & 7);
instruction.operands[0] = mem_oper;
instruction.operands[1] = OperandSpec::ImmI8;
instruction.operand_count = 2;
diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index 29c2750..b60ff34 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -6023,6 +6023,7 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T,
instruction.operand_count = 1;
},
1 => {
+ instruction.opcode = base_opcode_map((modrm >> 3) & 7);
instruction.operands[0] = mem_oper;
instruction.operands[1] = OperandSpec::ImmI8;
instruction.operand_count = 2;
diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs
index 33fc8c7..3b31dbb 100644
--- a/test/long_mode/mod.rs
+++ b/test/long_mode/mod.rs
@@ -1097,6 +1097,7 @@ fn test_prefixes() {
test_display(&[0x40, 0x32, 0xc5], "xor al, bpl");
test_invalid(&[0xf0, 0x33, 0xc0]);
test_display(&[0xf0, 0x31, 0x00], "lock xor [rax], eax");
+ test_display(&[0xf0, 0x80, 0x30, 0x00], "lock xor [rax], 0x0");
test_invalid(&[0xf0, 0xc7, 0x00, 0x00, 0x00, 0x00]);
}
diff --git a/test/protected_mode/mod.rs b/test/protected_mode/mod.rs
index c5c3c7b..84448ef 100644
--- a/test/protected_mode/mod.rs
+++ b/test/protected_mode/mod.rs
@@ -972,6 +972,7 @@ fn test_prefixes() {
test_display(&[0x66, 0x32, 0xc5], "xor al, ch");
test_invalid(&[0xf0, 0x33, 0xc0]);
test_display(&[0xf0, 0x31, 0x00], "lock xor [eax], eax");
+ test_display(&[0xf0, 0x80, 0x30, 0x00], "lock xor [eax], 0x0");
test_invalid(&[0xf0, 0xc7, 0x00, 0x00, 0x00, 0x00]);
}