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authoriximeow <me@iximeow.net>2021-05-07 00:12:37 -0700
committeriximeow <me@iximeow.net>2021-05-07 00:12:37 -0700
commitbf4dc7ee2fd352a01deda314da82af588dd50952 (patch)
tree364da3ca93d7b61f3eaf129b8f1175a27da86331
parent2ad06203b892a1b6bc3ea9769066d1a959aef690 (diff)
remove dead OperandSpec variants
-rw-r--r--src/long_mode/mod.rs16
-rw-r--r--src/protected_mode/mod.rs3
2 files changed, 0 insertions, 19 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index abb9723..57508e4 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -463,8 +463,6 @@ impl OperandSpec {
OperandSpec::Deref_rdi |
OperandSpec::RegDisp |
OperandSpec::RegScale |
- OperandSpec::RegIndexBase |
- OperandSpec::RegIndexBaseDisp |
OperandSpec::RegScaleDisp |
OperandSpec::RegIndexBaseScale |
OperandSpec::RegIndexBaseScaleDisp => {
@@ -476,8 +474,6 @@ impl OperandSpec {
OperandSpec::ImmI64 |
OperandSpec::ImmU8 |
OperandSpec::ImmU16 |
- OperandSpec::ImmU32 |
- OperandSpec::ImmU64 |
OperandSpec::RegRRR |
OperandSpec::RegMMM |
OperandSpec::RegVex |
@@ -514,9 +510,7 @@ impl Operand {
OperandSpec::ImmI16 => Operand::ImmediateI16(inst.imm as i16),
OperandSpec::ImmU16 => Operand::ImmediateU16(inst.imm as u16),
OperandSpec::ImmI32 => Operand::ImmediateI32(inst.imm as i32),
- OperandSpec::ImmU32 => Operand::ImmediateU32(inst.imm as u32),
OperandSpec::ImmI64 => Operand::ImmediateI64(inst.imm as i64),
- OperandSpec::ImmU64 => Operand::ImmediateU64(inst.imm as u64),
OperandSpec::ImmInDispField => Operand::ImmediateU16(inst.disp as u16),
OperandSpec::DispU32 => Operand::DisplacementU32(inst.disp as u32),
OperandSpec::DispU64 => Operand::DisplacementU64(inst.disp as u64),
@@ -535,12 +529,6 @@ impl Operand {
OperandSpec::RegScale => {
Operand::RegScale(inst.sib_index, inst.scale)
}
- OperandSpec::RegIndexBase => {
- Operand::RegIndexBase(inst.modrm_mmm, inst.sib_index)
- }
- OperandSpec::RegIndexBaseDisp => {
- Operand::RegIndexBaseDisp(inst.modrm_mmm, inst.sib_index, inst.disp as i32)
- }
OperandSpec::RegScaleDisp => {
Operand::RegScaleDisp(inst.sib_index, inst.scale, inst.disp as i32)
}
@@ -2034,8 +2022,6 @@ enum OperandSpec {
ImmI64,
ImmU8,
ImmU16,
- ImmU32,
- ImmU64,
// ENTER is a two-immediate instruction, where the first immediate is stored in the disp field.
// for this case, a second immediate-style operand is needed.
// turns out `insertq` and `extrq` are also two-immediate instructions, so this is generalized
@@ -2048,8 +2034,6 @@ enum OperandSpec {
Deref_rdi,
RegDisp,
RegScale,
- RegIndexBase,
- RegIndexBaseDisp,
RegScaleDisp,
RegIndexBaseScale,
RegIndexBaseScaleDisp
diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index 583007b..10aba56 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -419,7 +419,6 @@ impl OperandSpec {
OperandSpec::ImmI32 |
OperandSpec::ImmU8 |
OperandSpec::ImmU16 |
- OperandSpec::ImmU32 |
OperandSpec::RegRRR |
OperandSpec::RegMMM |
OperandSpec::RegVex |
@@ -456,7 +455,6 @@ impl Operand {
OperandSpec::ImmI16 => Operand::ImmediateI16(inst.imm as i16),
OperandSpec::ImmU16 => Operand::ImmediateU16(inst.imm as u16),
OperandSpec::ImmI32 => Operand::ImmediateI32(inst.imm as i32),
- OperandSpec::ImmU32 => Operand::ImmediateU32(inst.imm as u32),
OperandSpec::ImmInDispField => Operand::ImmediateU16(inst.disp as u16),
OperandSpec::DispU16 => Operand::DisplacementU16(inst.disp as u16),
OperandSpec::DispU32 => Operand::DisplacementU32(inst.disp),
@@ -1948,7 +1946,6 @@ enum OperandSpec {
ImmI32,
ImmU8,
ImmU16,
- ImmU32,
// ENTER is a two-immediate instruction, where the first immediate is stored in the disp field.
// for this case, a second immediate-style operand is needed.
// turns out `insertq` and `extrq` are also two-immediate instructions, so this is generalized