working through a bunch of avx512 stuff, regspec constructors are const

author: iximeow <me@iximeow.net> 2026-05-08 01:19:33 +0000
committer: iximeow <me@iximeow.net> 2026-05-25 01:43:55 +0000
commit: f900cfe558b97d187226c6e0791ad8992ba8f4a0 (patch)
tree: 8909e645eed396945cba92e9e1a370579d9ce26a
parent: 307d39dedfabaa0a0400ba62cd9a418d3f94a582 (diff)
10 files changed, 840 insertions, 207 deletions
diff --git a/CHANGELOG b/CHANGELOG
index f8197d0..b42570b 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -7,6 +7,8 @@
     even when their corresponding extension is not selected.
 * added uarch-specific decoders for Zen 2, Zen 3, Zen 4, and Zen 5
 * removed 3DNow support from AMD uarch-specific decoders after K10
+* RegSpec register helpers to construct RegSpec from register numbers are now const fn
+  (RegSpec::xmm, RegSpec::q, RegSpec::d, RegSpec::st, etc)
 * for uarch-specific decoding, there is now a feature bit for Intel Key Locker. this corrects an
   issue where Key Locker instructions would decode under AMD-specific decoders.
 * push-immediate, pushf, popf, enter, leave, and xlat now all report a correct memory
@@ -32,6 +34,8 @@
   always decoded as ymm.
 * vmaskmovqdu now reports a memory access size for the implied write to ds:[rdi/edi/di].
 * correct swapped operand order of 0xD6-opcode movq. in 32/16-bit, fix this opcode being decoded as vmovd.
+* reject so many invalid AVX512 encodings (instructions which do not support broadcast,
+  or rounding, or require W=0/W=1, etc).
 * some instructions (such as invept, invvpid) were accepted by uarch-specific
   deocders when they should not have been.
 
diff --git a/src/isa_settings.rs b/src/isa_settings.rs
index 76eb795..96233f3 100644
--- a/src/isa_settings.rs
+++ b/src/isa_settings.rs
@@ -77,12 +77,66 @@ macro_rules! gen_isa_settings {
             )*
         }
 
+        // only present in Knights Mill
+        static AVX512_4FMAPS: &[Opcode] = &[
+            Opcode::V4FMADDPS,
+            Opcode::V4FNMADDPS,
+            Opcode::V4FMADDSS,
+            Opcode::V4FNMADDSS,
+        ];
+
+        // only present in Knights Mill
+        static AVX512_4VNNIW: &[Opcode] = &[
+            Opcode::VP4DPWSSDS,
+            Opcode::VP4DPWSSD,
+        ];
+
+        // only present in Knights *?
+        static AVX512_ER: &[Opcode] = &[
+            Opcode::VEXP2PD,
+            Opcode::VEXP2PS,
+            Opcode::VRCP28PD,
+            Opcode::VRCP28PS,
+            Opcode::VRCP28SD,
+            Opcode::VRCP28SS,
+            Opcode::VRSQRT28PD,
+            Opcode::VRSQRT28PS,
+            Opcode::VRSQRT28SD,
+            Opcode::VRSQRT28SS,
+        ];
+
         /// optionally reject or reinterpret instruction according to settings for this decode
         /// operation.
         pub(crate) fn revise_instruction(settings: &$featureful_decoder, inst: &mut $inst_ty) -> Result<(), $decode_err> {
             if inst.prefixes.evex().is_some() {
+                // TODO: this happens to be the set of features on a Zen 5 processor..
+                let avx512_baseline = settings.avx512_f()
+                    && settings.avx512_dq()
+                    && settings.avx512_fma()
+                    && settings.avx512_cd()
+                    && settings.avx512_bw()
+                    && settings.avx512_vl()
+                    && settings.avx512_vbmi()
+                    && settings.avx512_vbmi2()
+                    && settings.avx512_vnni()
+                    && settings.avx512_bitalg()
+                    && settings.avx512_vpopcntdq();
+
                 if !settings.avx512() {
-                    return Err(<$decode_err>::InvalidOpcode);
+                    if !settings.avx512_4vnniw() && AVX512_4VNNIW.contains(&inst.opcode) {
+                        return Err(<$decode_err>::InvalidOpcode);
+                    } else if !settings.avx512_4fmaps() && AVX512_4FMAPS.contains(&inst.opcode) {
+                        return Err(<$decode_err>::InvalidOpcode);
+                    } else if !settings.avx512_er() && AVX512_ER.contains(&inst.opcode) {
+                        return Err(<$decode_err>::InvalidOpcode);
+                    } else if avx512_baseline {
+                        // TODO: hack around missing avx feature set specificity.
+                        return Ok(());
+                    } else {
+                        // TODO: if settings.with_avx512(false) == *settings {
+                        // truly no AVX512 at all..
+                        return Err(<$decode_err>::InvalidOpcode);
+                    }
                 } else {
                     return Ok(());
                 }
@@ -785,6 +839,11 @@ macro_rules! gen_isa_settings {
                         return Err(<$decode_err>::InvalidOpcode);
                     }
                 }
+                <$opcode>::HRESET => {
+                    if !settings.hreset() {
+                        return Err(<$decode_err>::InvalidOpcode);
+                    }
+                }
 
                 other => {
                     if !settings.bmi1() {
@@ -830,6 +889,8 @@ macro_rules! gen_arch_isa_settings {
             avx512_vbmi2, with_avx512_vbmi2 = 21;
             avx512_vl, with_avx512_vl = 22;
             avx512_vpopcntdq, with_avx512_vpopcntdq = 23;
+            // TODO: VP2INTERSECTD
+            // avx512_vp2intersectd, with_avx512_vp2intersectq = ;
             avx_vnni, with_avx_vnni = 24;
             bmi1, with_bmi1 = 25;
             #[doc="`bmi2` indicates support for the `BZHI`, `MULX`, `PDEP`, `PEXT`, `RORX`, `SARX`, `SHRX`, "]
@@ -957,6 +1018,7 @@ macro_rules! gen_arch_isa_settings {
             avx512_ifma, with_avx512_ifma = 110;
 
             keylocker, with_keylocker = 111;
+            hreset, with_hreset = 112;
 
             {
                 sse4 = {
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index b262308..df7d025 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -134,10 +134,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for x87 register `st(num)`
     #[inline]
-    pub fn st(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x87 reg st({})", num);
-        }
+    pub const fn st(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x87 reg");
 
         RegSpec {
             num,
@@ -147,10 +145,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for xmm reg `num`
     #[inline]
-    pub fn xmm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 xmm reg {}", num);
-        }
+    pub const fn xmm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 xmm reg");
 
         RegSpec {
             num,
@@ -160,10 +156,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for ymm reg `num`
     #[inline]
-    pub fn ymm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 ymm reg {}", num);
-        }
+    pub const fn ymm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 ymm reg");
 
         RegSpec {
             num,
@@ -173,10 +167,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for zmm reg `num`
     #[inline]
-    pub fn zmm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 zmm reg {}", num);
-        }
+    pub const fn zmm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 zmm reg");
 
         RegSpec {
             num,
@@ -186,10 +178,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for qword reg `num`
     #[inline]
-    pub fn q(num: u8) -> RegSpec {
-        if num >= 16 {
-            panic!("invalid x86 qword reg {}", num);
-        }
+    pub const fn q(num: u8) -> RegSpec {
+        assert!(num < 16, "invalid x86 qword reg");
 
         RegSpec {
             num,
@@ -199,10 +189,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for mask reg `num`
     #[inline]
-    pub fn mask(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 mask reg {}", num);
-        }
+    pub const fn mask(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 mask reg");
 
         RegSpec {
             num,
@@ -212,10 +200,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for dword reg `num`
     #[inline]
-    pub fn d(num: u8) -> RegSpec {
-        if num >= 16 {
-            panic!("invalid x86 dword reg {}", num);
-        }
+    pub const fn d(num: u8) -> RegSpec {
+        assert!(num < 16, "invalid x86 dword reg");
 
         RegSpec {
             num,
@@ -225,10 +211,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for word reg `num`
     #[inline]
-    pub fn w(num: u8) -> RegSpec {
-        if num >= 16 {
-            panic!("invalid x86 word reg {}", num);
-        }
+    pub const fn w(num: u8) -> RegSpec {
+        assert!(num < 16, "invalid x86 word reg");
 
         RegSpec {
             num,
@@ -238,10 +222,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for non-rex byte reg `num`
     #[inline]
-    pub fn rb(num: u8) -> RegSpec {
-        if num >= 16 {
-            panic!("invalid x86 rex-byte reg {}", num);
-        }
+    pub const fn rb(num: u8) -> RegSpec {
+        assert!(num < 16, "invalid x86 rex-byte reg");
 
         let bank = if num < 4 {
             RegisterBank::B
@@ -257,10 +239,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for non-rex byte reg `num`
     #[inline]
-    pub fn b(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 non-rex byte reg {}", num);
-        }
+    pub const fn b(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 non-rex-byte reg");
 
         RegSpec {
             num,
diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index a59216f..d5690b8 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -133,10 +133,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for x87 register `st(num)`
     #[inline]
-    pub fn st(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x87 reg st({})", num);
-        }
+    pub const fn st(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x87 reg");
 
         RegSpec {
             num,
@@ -146,10 +144,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for xmm reg `num`
     #[inline]
-    pub fn xmm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 xmm reg {}", num);
-        }
+    pub const fn xmm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 xmm reg");
 
         RegSpec {
             num,
@@ -159,10 +155,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for ymm reg `num`
     #[inline]
-    pub fn ymm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 ymm reg {}", num);
-        }
+    pub const fn ymm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 ymm reg");
 
         RegSpec {
             num,
@@ -172,10 +166,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for zmm reg `num`
     #[inline]
-    pub fn zmm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 zmm reg {}", num);
-        }
+    pub const fn zmm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 zmm reg");
 
         RegSpec {
             num,
@@ -185,10 +177,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for mask reg `num`
     #[inline]
-    pub fn mask(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 mask reg {}", num);
-        }
+    pub const fn mask(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 mask reg");
 
         RegSpec {
             num,
@@ -198,10 +188,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for dword reg `num`
     #[inline]
-    pub fn d(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 dword reg {}", num);
-        }
+    pub const fn d(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 dword reg");
 
         RegSpec {
             num,
@@ -211,10 +199,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for word reg `num`
     #[inline]
-    pub fn w(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 word reg {}", num);
-        }
+    pub const fn w(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 word reg");
 
         RegSpec {
             num,
@@ -224,10 +210,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for byte reg `num`
     #[inline]
-    pub fn b(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 byte reg {}", num);
-        }
+    pub const fn b(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 byte reg");
 
         RegSpec {
             num,
diff --git a/src/real_mode/mod.rs b/src/real_mode/mod.rs
index 2530c1d..6c7365c 100644
--- a/src/real_mode/mod.rs
+++ b/src/real_mode/mod.rs
@@ -133,10 +133,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for x87 register `st(num)`
     #[inline]
-    pub fn st(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x87 reg st({})", num);
-        }
+    pub const fn st(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x87 reg");
 
         RegSpec {
             num,
@@ -146,10 +144,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for xmm reg `num`
     #[inline]
-    pub fn xmm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 xmm reg {}", num);
-        }
+    pub const fn xmm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 xmm reg");
 
         RegSpec {
             num,
@@ -159,10 +155,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for ymm reg `num`
     #[inline]
-    pub fn ymm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 ymm reg {}", num);
-        }
+    pub const fn ymm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 ymm reg");
 
         RegSpec {
             num,
@@ -172,10 +166,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for zmm reg `num`
     #[inline]
-    pub fn zmm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 zmm reg {}", num);
-        }
+    pub const fn zmm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 zmm reg");
 
         RegSpec {
             num,
@@ -185,10 +177,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for mask reg `num`
     #[inline]
-    pub fn mask(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 mask reg {}", num);
-        }
+    pub const fn mask(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 mask reg");
 
         RegSpec {
             num,
@@ -198,10 +188,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for dword reg `num`
     #[inline]
-    pub fn d(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 dword reg {}", num);
-        }
+    pub const fn d(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 dword reg");
 
         RegSpec {
             num,
@@ -211,10 +199,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for word reg `num`
     #[inline]
-    pub fn w(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 word reg {}", num);
-        }
+    pub const fn w(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 word reg");
 
         RegSpec {
             num,
@@ -224,10 +210,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for byte reg `num`
     #[inline]
-    pub fn b(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 byte reg {}", num);
-        }
+    pub const fn b(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 byte reg");
 
         RegSpec {
             num,
diff --git a/src/shared/evex.in b/src/shared/evex.in
index 0aa7d95..07c82e5 100644
--- a/src/shared/evex.in
+++ b/src/shared/evex.in
@@ -1,6 +1,7 @@
 use super::OperandSpec;
 use super::FieldDescription;
 use super::InnerDescription;
+use super::Prefixes;
 
 use yaxpeax_arch::annotation::DescriptionSink;
 
@@ -312,6 +313,23 @@ fn check_mask_reg(inst: &Instruction) -> Result<(), DecodeError> {
 }
 
 #[inline(always)]
+fn check_allowed_zero_merge(prefixes: &Prefixes, oper: OperandSpec) -> Result<(), DecodeError> {
+  if prefixes.evex_unchecked().merge() {
+    // if evex.z is set
+
+    if oper.is_memory() {
+      // quoth APM,
+      // > 3.2.4 Exceptions Caused by Illegal EVEX encodings
+      // > ..
+      // > EVEX.z == 1 ... Instructions that do not specify {z} ... #UD
+      return Err(DecodeError::InvalidOperand);
+    }
+  }
+
+  Ok(())
+}
+
+#[inline(always)]
 fn apply_broadcast(inst: &mut Instruction, item_size: u8, reg_size: u8) {
   if inst.prefixes.evex_unchecked().broadcast() {
     inst.mem_size = item_size;
@@ -436,6 +454,8 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().vex().w() {
         if instruction.opcode == Opcode::VRSQRT14SS {
           instruction.opcode = Opcode::VRSQRT14SD;
+        } else if instruction.opcode == Opcode::VRCP14SS {
+          instruction.opcode = Opcode::VRCP14SD;
         }
       }
 
@@ -471,6 +491,10 @@ pub(crate) fn read_evex_operands<
       } else {
         if instruction.prefixes.evex_unchecked().broadcast() {
           return Err(DecodeError::InvalidOpcode);
+        } else {
+          if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+            return Err(DecodeError::InvalidOpcode);
+          }
         }
         instruction.mem_size = 8;
       }
@@ -488,12 +512,6 @@ pub(crate) fn read_evex_operands<
 
       instruction.operand_count = 3;
 
-      if instruction.prefixes.evex_unchecked().vex().w() {
-        if instruction.opcode == Opcode::VGETEXPSS {
-          instruction.opcode = Opcode::VGETEXPSD;
-        }
-      }
-
       if let OperandSpec::RegMMM = mem_oper {
         if instruction.prefixes.evex_unchecked().broadcast() {
           instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
@@ -554,7 +572,10 @@ pub(crate) fn read_evex_operands<
           instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
         }
       } else {
-        if instruction.prefixes.evex_unchecked().broadcast() {
+        deny_broadcast(instruction)?;
+
+        if instruction.prefixes.evex_unchecked().lp() &&
+          instruction.prefixes.evex_unchecked().vex().l() {
           return Err(DecodeError::InvalidOpcode);
         }
 
@@ -763,6 +784,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::G_V_Ed_xmm_imm8_W0 => {
       deny_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -809,6 +832,9 @@ pub(crate) fn read_evex_operands<
           return Err(DecodeError::InvalidOperand);
         }
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       instruction.operands[1] = OperandSpec::RegVex;
@@ -817,6 +843,8 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::G_V_xmm_Edq_imm8 => {
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let (sz, bank) = if instruction.prefixes.evex_unchecked().vex().w() {
         if isa_has_qwords() {
@@ -847,6 +875,8 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::G_V_xmm_Ebd_imm8 => {
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -900,25 +930,10 @@ pub(crate) fn read_evex_operands<
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
-      instruction.operand_count = 3;
-
-      set_reg_sizes_from_ll(instruction)?;
-    }
-    generated::EVEXOperandCode::M_G_LL_W0 => {
-      deny_vex_reg(instruction)?;
-      deny_mask_reg(instruction)?;
-
-      instruction.mem_size = regs_size(instruction);
-
-      let modrm = read_modrm(words)?;
-      set_rrr(instruction, modrm);
-      let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
       if mem_oper == OperandSpec::RegMMM {
-        return Err(DecodeError::InvalidOperand);
+        deny_broadcast(instruction)?;
       }
-      instruction.operands[0] = mem_oper;
-      instruction.operands[1] = OperandSpec::RegRRR;
-      instruction.operand_count = 2;
+      instruction.operand_count = 3;
 
       set_reg_sizes_from_ll(instruction)?;
     }
@@ -926,6 +941,8 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
@@ -945,12 +962,14 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.operands[0] = mem_oper.masked();
       instruction.operands[1] = OperandSpec::RegRRR;
       instruction.operand_count = 2;
@@ -960,6 +979,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::G_Ed_xmm_sae_W0 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
       // vucomiss and vcomiss both are W=0
       ensure_W(instruction, 0)?;
 
@@ -968,12 +988,18 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       instruction.regs[0].bank = RegisterBank::X;
 
       // in specific support of vcomisd/vucomisd
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       instruction.operands[1] = mem_oper;
@@ -981,7 +1007,8 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Gm_Eq_xmm_sae_W1 => {
       deny_vex_reg(instruction)?;
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
       // vucomisd and vcomisd both are W=1
       ensure_W(instruction, 1)?;
 
@@ -990,12 +1017,18 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       instruction.regs[0].bank = RegisterBank::X;
 
       // in specific support of vcomisd/vucomisd
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       instruction.operands[1] = mem_oper;
@@ -1005,6 +1038,7 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
@@ -1073,6 +1107,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Maskm_V_E_LL_imm8_sae_bcast_W1 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -1126,7 +1161,7 @@ pub(crate) fn read_evex_operands<
         }
       } else {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
-        apply_broadcast(instruction, 8, sz);
+        apply_broadcast(instruction, 4, sz);
         set_reg_sizes_from_ll(instruction)?;
       }
     }
@@ -1365,9 +1400,8 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::G_V_E_LL => {
       deny_mask_reg(instruction)?;
-      if [Opcode::VAESDECLAST, Opcode::VAESDEC, Opcode::VAESENC, Opcode::VAESENCLAST].contains(&instruction.opcode) {
-        deny_z(instruction)?;
-      }
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -1444,6 +1478,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      if instruction.prefixes.evex_unchecked().broadcast() && !mem_oper.is_memory() {
+        return Err(DecodeError::InvalidOpcode);
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
@@ -1463,6 +1500,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = mem_oper;
       instruction.imm = read_imm_unsigned(words, 1)?;
@@ -1483,6 +1523,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = mem_oper;
       instruction.imm = read_imm_unsigned(words, 1)?;
@@ -1571,6 +1614,9 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if instruction.prefixes.evex_unchecked().broadcast() {
+        if mem_oper.is_memory() {
+           return Err(DecodeError::InvalidOperand);
+        }
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
         if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
@@ -1595,8 +1641,6 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().vex().w() {
         if instruction.opcode == Opcode::VSCALEFSS {
           instruction.opcode = Opcode::VSCALEFSD;
-        } else if instruction.opcode == Opcode::VRCP14SS {
-          instruction.opcode = Opcode::VRCP14SD;
         }
       }
 
@@ -1604,6 +1648,9 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if instruction.prefixes.evex_unchecked().broadcast() {
+        if mem_oper.is_memory() {
+          return Err(DecodeError::InvalidOpcode);
+        };
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
       } else {
         if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
@@ -1626,6 +1673,44 @@ pub(crate) fn read_evex_operands<
       }
       set_reg_sizes(instruction, RegisterBank::X);
     }
+    generated::EVEXOperandCode::Gm_V_Ed_xmm_sae_noround => {
+      check_mask_reg(instruction)?;
+
+      if instruction.prefixes.evex_unchecked().vex().w() {
+        if instruction.opcode == Opcode::VGETEXPSS {
+          instruction.opcode = Opcode::VGETEXPSD;
+        }
+      }
+
+      let modrm = read_modrm(words)?;
+      set_rrr(instruction, modrm);
+      let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if instruction.prefixes.evex_unchecked().broadcast() {
+        if mem_oper.is_memory() {
+          return Err(DecodeError::InvalidOpcode);
+        };
+        instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
+      } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOperand);
+        }
+        instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
+      }
+      instruction.operands[1] = OperandSpec::RegVex;
+      instruction.operands[2] = mem_oper;
+      instruction.operand_count = 3;
+
+      if mem_oper == OperandSpec::RegMMM {
+        instruction.mem_size = 0;
+      } else {
+        if instruction.prefixes.evex_unchecked().vex().w() {
+          instruction.mem_size = 8;
+        } else {
+          instruction.mem_size = 4;
+        }
+      }
+      set_reg_sizes(instruction, RegisterBank::X);
+    }
     generated::EVEXOperandCode::Gm_V_Ed_xmm_sae_W0 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
@@ -1665,6 +1750,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         if instruction.prefixes.evex_unchecked().broadcast() {
           // sae sets this to `vcvtps2ph ymm, zmm, imm8`
@@ -1698,6 +1784,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         if instruction.prefixes.evex_unchecked().broadcast() {
           // sae sets this to `vcvtps2ph ymm, zmm, imm8`
@@ -1732,6 +1819,7 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       instruction.regs[0].bank = RegisterBank::Z;
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         if instruction.prefixes.evex_unchecked().broadcast() {
           instruction.operands[0] = OperandSpec::RegMMM_maskmerge_sae_noround;
@@ -1739,6 +1827,9 @@ pub(crate) fn read_evex_operands<
           instruction.operands[0] = OperandSpec::RegMMM_maskmerge;
         }
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         if instruction.prefixes.evex_unchecked().broadcast() {
           return Err(DecodeError::InvalidOperand);
         } else {
@@ -1847,6 +1938,7 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       instruction.regs[0].bank = RegisterBank::Z;
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.mem_size = 32;
       instruction.operands[0] = mem_oper.masked();
       instruction.operands[1] = OperandSpec::RegRRR;
@@ -1966,6 +2058,7 @@ pub(crate) fn read_evex_operands<
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2001,8 +2094,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Gm_ymm_E_xmm_W0 => {
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
-      ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2039,6 +2132,7 @@ pub(crate) fn read_evex_operands<
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2080,6 +2174,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Z;
       instruction.mem_size = 32;
       instruction.operands[0] = mem_oper.masked();
@@ -2095,6 +2190,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Z;
       instruction.mem_size = 16;
       instruction.operands[0] = mem_oper.masked();
@@ -2110,6 +2206,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Y;
       instruction.mem_size = 16;
       instruction.operands[0] = mem_oper.masked();
@@ -2125,6 +2222,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Z;
       instruction.mem_size = 8;
       instruction.operands[0] = mem_oper.masked();
@@ -2140,6 +2238,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::X;
       instruction.mem_size = 8;
       instruction.operands[0] = mem_oper.masked();
@@ -2155,6 +2254,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Y;
       instruction.mem_size = 4;
       instruction.operands[0] = mem_oper.masked();
@@ -2170,6 +2270,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::X;
       instruction.mem_size = 4;
       instruction.operands[0] = mem_oper.masked();
@@ -2185,6 +2286,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::X;
       instruction.mem_size = 2;
       instruction.operands[0] = mem_oper.masked();
@@ -2200,6 +2302,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Y;
       instruction.mem_size = 8;
       instruction.operands[0] = mem_oper.masked();
@@ -2408,6 +2511,7 @@ pub(crate) fn read_evex_operands<
         instruction.regs[0].bank = RegisterBank::Y;
       }
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.mem_size = 16;
       instruction.operands[0] = mem_oper.masked();
       instruction.operands[1] = OperandSpec::RegRRR;
@@ -2534,32 +2638,12 @@ pub(crate) fn read_evex_operands<
       instruction.operands[3] = OperandSpec::ImmU8;
       instruction.operand_count = 4;
     }
-    generated::EVEXOperandCode::VMOVQ_G_Ed_xmm => {
-      deny_mask_reg(instruction)?;
-      deny_vex_reg(instruction)?;
-      ensure_W(instruction, 1)?;
-      deny_broadcast(instruction)?;
-
-      let modrm = read_modrm(words)?;
-      set_rrr(instruction, modrm);
-      instruction.regs[0].bank = RegisterBank::X;
-      let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
-
-      if mem_oper == OperandSpec::RegMMM {
-        instruction.mem_size = 0;
-      } else {
-        instruction.mem_size = 8;
-      }
-
-      instruction.operands[0] = OperandSpec::RegRRR;
-      instruction.operands[1] = mem_oper;
-      instruction.operand_count = 2;
-    }
     generated::EVEXOperandCode::VMOVQ_Ed_G_xmm => {
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 1)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2581,6 +2665,7 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 1)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2599,6 +2684,7 @@ pub(crate) fn read_evex_operands<
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2630,6 +2716,7 @@ pub(crate) fn read_evex_operands<
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2659,6 +2746,11 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Mask_V_E_LL_bcast => {
       check_mask_reg(instruction)?;
+      deny_z(instruction)?;
+
+      if instruction.opcode == Opcode::VP2INTERSECTD {
+        deny_mask_reg(instruction)?;
+      }
 
       let sz = regs_size(instruction);
 
@@ -2680,6 +2772,7 @@ pub(crate) fn read_evex_operands<
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if mem_oper == OperandSpec::RegMMM {
         instruction.mem_size = 0;
+        deny_broadcast(instruction)?;
       }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
@@ -2696,6 +2789,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL_bcast_W1 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2704,7 +2798,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
         instruction.mem_size = 0;
       }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
@@ -2722,6 +2818,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL_bcast_W0 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2731,6 +2828,7 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
         instruction.mem_size = 0;
       }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
@@ -2773,6 +2871,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         instruction.mem_size = 0;
       }
@@ -2786,6 +2885,7 @@ pub(crate) fn read_evex_operands<
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2821,6 +2921,7 @@ pub(crate) fn read_evex_operands<
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2856,6 +2957,7 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 1)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2883,6 +2985,7 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2905,10 +3008,11 @@ pub(crate) fn read_evex_operands<
         return Err(DecodeError::InvalidOperand);
       }
     }
-    generated::EVEXOperandCode::G_E_LL_W0 => {
+    generated::EVEXOperandCode::G_M_LL_W0 => {
       deny_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2918,7 +3022,7 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if mem_oper == OperandSpec::RegMMM {
-        instruction.mem_size = 0;
+        return Err(DecodeError::InvalidOperand);
       }
       instruction.operands[0] = OperandSpec::RegRRR;
       instruction.operands[1] = mem_oper;
@@ -2926,20 +3030,20 @@ pub(crate) fn read_evex_operands<
 
       set_reg_sizes_from_ll(instruction)?;
     }
-    generated::EVEXOperandCode::E_G_LL_W0 => {
+    generated::EVEXOperandCode::M_G_LL_W0 => {
+      deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
-      let sz = regs_size(instruction);
-
-      instruction.mem_size = sz;
+      instruction.mem_size = regs_size(instruction);
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if mem_oper == OperandSpec::RegMMM {
-        instruction.mem_size = 0;
+        return Err(DecodeError::InvalidOperand);
       }
       instruction.operands[0] = mem_oper;
       instruction.operands[1] = OperandSpec::RegRRR;
@@ -2959,6 +3063,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         instruction.mem_size = 0;
       }
@@ -2990,6 +3095,7 @@ pub(crate) fn read_evex_operands<
       };
       instruction.regs[0].bank = r_sz;
       if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
         instruction.mem_size = 0;
         instruction.regs[1].bank = m_sz;
       } else {
@@ -3007,6 +3113,8 @@ pub(crate) fn read_evex_operands<
           instruction.opcode = Opcode::VPLZCNTQ;
         } else if instruction.opcode == Opcode::VRCP14PS {
           instruction.opcode = Opcode::VRCP14PD;
+        } else if instruction.opcode == Opcode::VRSQRT14PS {
+          instruction.opcode = Opcode::VRSQRT14PD;
         } else if instruction.opcode == Opcode::VPOPCNTD {
           instruction.opcode = Opcode::VPOPCNTQ;
         } else if instruction.opcode == Opcode::VPCONFLICTD {
@@ -3086,6 +3194,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Gm_LL_Ud => {
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
+      deny_broadcast(instruction)?;
 
       if instruction.prefixes.evex_unchecked().vex().w() && isa_has_qwords() {
         if instruction.opcode == Opcode::VPBROADCASTD {
@@ -3120,6 +3229,7 @@ pub(crate) fn read_evex_operands<
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_broadcast(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3355,8 +3465,6 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().vex().w() {
         if instruction.opcode == Opcode::VGETEXPPS {
           instruction.opcode = Opcode::VGETEXPPD;
-        } else if instruction.opcode == Opcode::VRSQRT14PS {
-          instruction.opcode = Opcode::VRSQRT14PD;
         }
       }
 
@@ -3380,11 +3488,7 @@ pub(crate) fn read_evex_operands<
             4
           }, sz);
         } else {
-          if instruction.opcode == Opcode::VSQRTPS || instruction.opcode == Opcode::VCVTPS2DQ {
-            instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
-          } else {
-            instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
-          }
+          instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
           set_reg_sizes(instruction, RegisterBank::Z);
         }
       } else {
@@ -3520,6 +3624,7 @@ pub(crate) fn read_evex_operands<
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3546,6 +3651,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL => {
       check_mask_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3594,6 +3700,10 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp()
+          && instruction.prefixes.evex_unchecked().vex().l() {
+            return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       }
       instruction.operands[1] = OperandSpec::RegVex;
@@ -3626,6 +3736,10 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp()
+          && instruction.prefixes.evex_unchecked().vex().l() {
+            return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       }
       instruction.operands[1] = OperandSpec::RegVex;
@@ -3644,6 +3758,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL_imm8 => {
       check_mask_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
       instruction.mem_size = sz;
@@ -3718,6 +3833,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_E_LL_imm8_bcast => {
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3763,6 +3879,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL_imm8_sae_bcast_W0 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3809,6 +3926,7 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Mask_V_E_LL_imm8_bcast => {
       check_mask_reg(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3890,6 +4008,9 @@ pub(crate) fn read_evex_operands<
       apply_broadcast(instruction, item_size, sz);
 
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegVex_maskmerge;
       instruction.operands[1] = mem_oper;
       instruction.imm = read_imm_unsigned(words, 1)?;
@@ -3978,17 +4099,14 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Gm_V_E_LL_imm8_W0 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_broadcast(instruction)?;
 
       let sz = regs_size(instruction);
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
-      if mem_oper == OperandSpec::RegMMM {
-        deny_broadcast(instruction)?;
-      } else {
-        instruction.mem_size = sz;
-      }
+      instruction.mem_size = sz;
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
@@ -4013,6 +4131,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
@@ -4023,7 +4144,9 @@ pub(crate) fn read_evex_operands<
       set_reg_sizes_from_ll(instruction)?;
     }
     generated::EVEXOperandCode::G_V_E_LL_imm8 => {
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
@@ -4041,6 +4164,7 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Gm_V_E_LL_imm8 => {
       check_mask_reg(instruction)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
@@ -4067,6 +4191,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
@@ -4235,6 +4362,7 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::VCVTPH2PS => {
       check_mask_reg(instruction)?;
+      ensure_W(instruction, 0)?;
       deny_vex_reg(instruction)?;
 
       if instruction.opcode == Opcode::VCVTPS2PD {
@@ -4248,6 +4376,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if instruction.opcode == Opcode::VCVTPH2PS && mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = mem_oper;
       instruction.operand_count = 2;
@@ -4439,6 +4570,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VCVTTPD2DQ => {
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
+      ensure_W(instruction, 1)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4527,6 +4659,15 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if !instruction.prefixes.evex_unchecked().broadcast() {
+        if instruction.prefixes.evex_unchecked().lp() {
+          if instruction.prefixes.evex_unchecked().vex().l() {
+            return Err(DecodeError::InvalidOperand);
+          }
+        }
+      } else if mem_oper.is_memory() {
+        return Err(DecodeError::InvalidOperand);
+      }
 
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
@@ -4673,6 +4814,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Edd_G_xmm_imm8 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4734,6 +4877,9 @@ pub(crate) fn read_evex_operands<
           }
         }
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         if instruction.prefixes.evex_unchecked().broadcast() {
           return Err(DecodeError::InvalidOpcode);
         }
@@ -4748,6 +4894,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VEXTRACTPS => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4768,6 +4916,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Ewd_G_xmm_imm8 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4788,6 +4938,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Ebd_G_xmm_imm8 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4840,6 +4992,10 @@ pub(crate) fn read_evex_operands<
       if let OperandSpec::RegMMM = mem_oper {
         instruction.mem_size = 0;
       } else{
+        deny_broadcast(instruction)?;
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.mem_size = item_size;
       }
       if instruction.prefixes.evex_unchecked().broadcast() {
@@ -4857,13 +5013,18 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Gm_V_E_xmm_imm8_sae_W1 => {
       ensure_W(instruction, 1)?;
+      check_mask_reg(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if let OperandSpec::RegMMM = mem_oper {
         /* no mem size */
-      } else{
+      } else {
+        deny_broadcast(instruction)?;
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.mem_size = 8;
       }
       if instruction.prefixes.evex_unchecked().broadcast() {
@@ -4918,6 +5079,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VMOVSD_10 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4940,10 +5102,12 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VMOVSD_11 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.operands[0] = mem_oper.masked();
       if mem_oper == OperandSpec::RegMMM {
         instruction.operands[1] = OperandSpec::RegVex;
@@ -4962,12 +5126,16 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VMOVSS_10 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       if mem_oper == OperandSpec::RegMMM {
+        if instruction.prefixes.evex_unchecked().broadcast() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[1] = OperandSpec::RegVex;
         instruction.operands[2] = mem_oper;
         instruction.operand_count = 3;
@@ -4984,10 +5152,12 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VMOVSS_11 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.operands[0] = mem_oper.masked();
       if mem_oper == OperandSpec::RegMMM {
         instruction.operands[1] = OperandSpec::RegVex;
@@ -5004,12 +5174,15 @@ pub(crate) fn read_evex_operands<
       set_reg_sizes(instruction, RegisterBank::X);
     }
     generated::EVEXOperandCode::VCVTSI2SS => {
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
       deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       if instruction.prefixes.evex_unchecked().broadcast() && mem_oper == OperandSpec::RegMMM {
         if (!instruction.prefixes.evex_unchecked().vex().w() || !isa_has_qwords()) && instruction.opcode == Opcode::VCVTSI2SD {
           instruction.operands[0] = OperandSpec::RegRRR;
@@ -5017,6 +5190,9 @@ pub(crate) fn read_evex_operands<
           instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
         }
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       instruction.operands[1] = OperandSpec::RegVex;
@@ -5049,15 +5225,21 @@ pub(crate) fn read_evex_operands<
       }
     }
     generated::EVEXOperandCode::VCVTTSS2SI => {
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
       deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       if instruction.prefixes.evex_unchecked().vex().w() {
@@ -5076,15 +5258,21 @@ pub(crate) fn read_evex_operands<
       instruction.operand_count = 2;
     }
     generated::EVEXOperandCode::VCVTSS2SI => {
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
       deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       if instruction.prefixes.evex_unchecked().vex().w() {
@@ -5105,6 +5293,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Operands_12_W0 => {
       deny_mask_reg(instruction)?;
       deny_z(instruction)?;
+      deny_broadcast(instruction)?;
       ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
@@ -5130,6 +5319,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Operands_16_W0 => {
       deny_mask_reg(instruction)?;
       deny_z(instruction)?;
+      deny_broadcast(instruction)?;
       ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
diff --git a/src/shared/generated_evex.in b/src/shared/generated_evex.in
index b2ca667..3f3764b 100644
--- a/src/shared/generated_evex.in
+++ b/src/shared/generated_evex.in
@@ -506,7 +506,6 @@ pub(crate) enum EVEXOperandCode {
   Gm_U_zmm_imm8_sae_W0,
   Gm_V_E_LL_sae_W1,
   Gm_U_zmm_sae_W0,
-  E_G_LL_W0,
   Ebd_G_xmm_imm8,
   Edd_G_xmm_imm8,
   Edm_xmm_G_xmm_W0,
@@ -527,7 +526,7 @@ pub(crate) enum EVEXOperandCode {
   Eqm_xmm_G_zmm_W0,
   Ewd_G_xmm_imm8,
   Ewm_xmm_G_xmm_W0,
-  G_E_LL_W0,
+  G_M_LL_W0,
   G_Ed_xmm_sae_W0,
   G_LL_Mask,
   G_LL_Mask_W0,
@@ -593,6 +592,7 @@ pub(crate) enum EVEXOperandCode {
   Gm_V_Ed_xmm_sae,
   Gm_V_Ed_xmm_sae_W0,
   Gm_V_Ed_xmm_sae_bcast,
+  Gm_V_Ed_xmm_sae_noround,
   Gm_V_Ed_xmm_sae_noround_W0,
   Gm_V_Eq_xmm_sae_W1,
   Gm_V_LL_E_xmm,
@@ -666,7 +666,6 @@ pub(crate) enum EVEXOperandCode {
   VMOVD_7e,
   VMOVQ_7e,
   VMOVQ_Ed_G_xmm,
-  VMOVQ_G_Ed_xmm,
   VMOVSD_10,
   VMOVSD_11,
   VMOVSS_10,
@@ -675,15 +674,23 @@ pub(crate) enum EVEXOperandCode {
   VPINSRW,
 }
 
+// the APM and SDM describe the prefix bits as selecting no prefix, "66, f2, or f3" opcode extension.
+// however, this is *not the order those bits are interpreted in*. compare APM and SDM encodings and
+// you will see:
+// > 0b00 -> none,
+// > 0b01 -> 0x66,
+// > 0b10 -> 0xf3, // !!
+// > 0b11 -> 0xf2, // !!
+// hence the ordering of table names below.
 pub(crate) const TABLES: [&'static [(u8, [(super::Opcode, EVEXOperandCode); 4])]; 12] = [
   &EVEX_None_0f,
   &EVEX_66_0f,
-  &EVEX_f2_0f,
   &EVEX_f3_0f,
+  &EVEX_f2_0f,
   &DUMMY,
   &EVEX_66_0f38,
-  &EVEX_f2_0f38,
   &EVEX_f3_0f38,
+  &EVEX_f2_0f38,
   &DUMMY,
   &EVEX_66_0f3a,
   &DUMMY,
@@ -701,12 +708,12 @@ const EVEX_None_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 30] = [
   (0x15, [(super::Opcode::VUNPCKHPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VUNPCKHPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VUNPCKHPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x16, [(super::Opcode::Invalid, EVEXOperandCode::Operands_16_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x17, [(super::Opcode::VMOVHPS, EVEXOperandCode::Mq_G_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x28, [(super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0x28, [(super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x29, [(super::Opcode::VMOVAPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2b, [(super::Opcode::VMOVNTPS, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTPS, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTPS, EVEXOperandCode::M_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2e, [(super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0)]),
   (0x2f, [(super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0)]),
-  (0x51, [(super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast)]),
+  (0x51, [(super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0)]),
   (0x54, [(super::Opcode::VANDPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x55, [(super::Opcode::VANDNPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDNPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDNPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x56, [(super::Opcode::VORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -749,7 +756,7 @@ const EVEX_66_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 100] = [
   (0x58, [(super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
   (0x59, [(super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
   (0x5a, [(super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_xmm_E_xmm_sae_bcast_W1), (super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_xmm_E_ymm_sae_bcast_W1), (super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_ymm_E_zmm_sae_bcast_W1), (super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_ymm_U_zmm_sae_W1)]),
-  (0x5b, [(super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast)]),
+  (0x5b, [(super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast_W0)]),
   (0x5c, [(super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
   (0x5d, [(super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
   (0x5e, [(super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
@@ -806,7 +813,7 @@ const EVEX_66_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 100] = [
   (0xe4, [(super::Opcode::VPMULHUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xe5, [(super::Opcode::VPMULHW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xe6, [(super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ)]),
-  (0xe7, [(super::Opcode::VMOVNTDQ, EVEXOperandCode::E_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::E_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::E_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0xe7, [(super::Opcode::VMOVNTDQ, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::M_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xe8, [(super::Opcode::VPSUBSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xe9, [(super::Opcode::VPSUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xea, [(super::Opcode::VPMINSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -861,7 +868,7 @@ const EVEX_66_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 143] = [
   (0x27, [(super::Opcode::VPTESTMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VPTESTMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VPTESTMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x28, [(super::Opcode::VPMULDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x29, [(super::Opcode::VPCMPEQQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::VPCMPEQQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::VPCMPEQQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x2a, [(super::Opcode::VMOVNTDQA, EVEXOperandCode::G_E_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_E_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0x2a, [(super::Opcode::VMOVNTDQA, EVEXOperandCode::G_M_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_M_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_M_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2b, [(super::Opcode::VPACKUSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPACKUSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPACKUSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2c, [(super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]),
   (0x2d, [(super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae)]),
@@ -883,15 +890,15 @@ const EVEX_66_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 143] = [
   (0x3f, [(super::Opcode::VPMAXUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMAXUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMAXUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x40, [(super::Opcode::VPMULLD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMULLD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMULLD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x42, [(super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast)]),
-  (0x43, [(super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast)]),
+  (0x43, [(super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround)]),
   (0x44, [(super::Opcode::VPLZCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPLZCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPLZCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x45, [(super::Opcode::VPSRLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x46, [(super::Opcode::VPSRAVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRAVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRAVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x47, [(super::Opcode::VPSLLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSLLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSLLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x4c, [(super::Opcode::VRCP14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRCP14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRCP14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x4d, [(super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae)]),
-  (0x4e, [(super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x4f, [(super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm)]),
+  (0x4d, [(super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0x4e, [(super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0x4f, [(super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x50, [(super::Opcode::VPDPBUSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x51, [(super::Opcode::VPDPBUSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x52, [(super::Opcode::VPDPWSSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPWSSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPWSSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -1021,7 +1028,7 @@ const EVEX_66_0f3a: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 51] = [
   (0x56, [(super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae), (super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae), (super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae), (super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae)]),
   (0x57, [(super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae)]),
   (0x66, [(super::Opcode::VFPCLASSPS, EVEXOperandCode::Mask_E_LL_imm8_bcast), (super::Opcode::VFPCLASSPS, EVEXOperandCode::Mask_E_LL_imm8_bcast), (super::Opcode::VFPCLASSPS, EVEXOperandCode::Mask_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x67, [(super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8)]),
+  (0x67, [(super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x70, [(super::Opcode::VPSHLDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHLDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHLDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x71, [(super::Opcode::VPSHLDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPSHLDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPSHLDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x72, [(super::Opcode::VPSHRDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHRDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHRDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -1030,9 +1037,9 @@ const EVEX_66_0f3a: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 51] = [
   (0xcf, [(super::Opcode::VGF2P8AFFINEINVQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VGF2P8AFFINEINVQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VGF2P8AFFINEINVQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
 ];
 
-const EVEX_f2_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 26] = [
-  (0x10, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10)]),// W0
-  (0x11, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11)]),// W0
+const EVEX_f3_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 26] = [
+  (0x10, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W0
+  (0x11, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W0
   (0x12, [(super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x16, [(super::Opcode::VMOVSHDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSHDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSHDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2a, [(super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS)]),
@@ -1059,7 +1066,7 @@ const EVEX_f2_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 26] = [
   (0xe6, [(super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD)]),
 ];
 
-const EVEX_f2_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 28] = [
+const EVEX_f3_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 28] = [
   (0x10, [(super::Opcode::VPMOVUSWB, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSWB, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVUSWB, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x11, [(super::Opcode::VPMOVUSDB, EVEXOperandCode::Edm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSDB, EVEXOperandCode::Eqm_xmm_G_ymm_W0), (super::Opcode::VPMOVUSDB, EVEXOperandCode::Em_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x12, [(super::Opcode::VPMOVUSQB, EVEXOperandCode::Ewm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSQB, EVEXOperandCode::Edm_xmm_G_ymm_W0), (super::Opcode::VPMOVUSQB, EVEXOperandCode::Eqm_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -1090,9 +1097,9 @@ const EVEX_f2_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 28] = [
   (0x72, [(super::Opcode::VCVTNEPS2BF16, EVEXOperandCode::Operands_72_W0), (super::Opcode::VCVTNEPS2BF16, EVEXOperandCode::Operands_72_W0), (super::Opcode::VCVTNEPS2BF16, EVEXOperandCode::Operands_72_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
 ];
 
-const EVEX_f3_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 24] = [
-  (0x10, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10)]),// W1
-  (0x11, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11)]),// W1
+const EVEX_f2_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 23] = [
+  (0x10, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W1
+  (0x11, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W1
   (0x12, [(super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2a, [(super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS)]),
   (0x2c, [(super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae)]),
@@ -1104,20 +1111,19 @@ const EVEX_f3_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 24] = [
   (0x5c, [(super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]),
   (0x5d, [(super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]),// W1
   (0x5e, [(super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]),
-  (0x5f, [(super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae)]),// W1
+  (0x5f, [(super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]),// W1
   (0x6f, [(super::Opcode::VMOVDQU8, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x70, [(super::Opcode::VPSHUFLW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::VPSHUFLW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::VPSHUFLW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x78, [(super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae)]),
   (0x79, [(super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae)]),
   (0x7a, [(super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS)]),
   (0x7b, [(super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD), (super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD), (super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD), (super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD)]),
-  (0x7e, [(super::Opcode::VMOVQ, EVEXOperandCode::VMOVQ_G_Ed_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x7f, [(super::Opcode::VMOVDQU8, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Em_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xc2, [(super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1), (super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1), (super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1), (super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1)]),
   (0xe6, [(super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ)]),
 ];
 
-const EVEX_f3_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 8] = [
+const EVEX_f2_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 8] = [
   (0x52, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VP4DPWSSD, EVEXOperandCode::Gm_V_zmm_M_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x53, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VP4DPWSSDS, EVEXOperandCode::Gm_V_zmm_M_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x68, [(super::Opcode::VP2INTERSECTD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VP2INTERSECTD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VP2INTERSECTD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
diff --git a/test/long_mode/evex_generated.rs b/test/long_mode/evex_generated.rs
index 46d99a7..93dd69e 100644
--- a/test/long_mode/evex_generated.rs
+++ b/test/long_mode/evex_generated.rs
@@ -118,7 +118,9 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0xca], "vmovups xmm2{k5}, xmm1"); // VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0x0a], "vmovups xmmword [rdx], xmm1"); // VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x0a], "vmovups xmmword [rdx]{k5}, xmm1"); // VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0xca], "vmovhlps xmm1, xmm0, xmm2"); // VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x12, 0xca]); // no broadcast
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x0a], "vmovlps xmm1, xmm0, qword [rdx]"); // VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x13, 0x0a], "vmovlps qword [rdx], xmm1"); // VMOVLPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x14, 0x0a], "vunpcklps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -176,10 +178,12 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0x0a], "vunpckhps xmm1, xmm0, xmmword [rdx]"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0x0a], "vunpckhps xmm1{k5}, xmm0, xmmword [rdx]"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0xca], "vmovlhps xmm1, xmm0, xmm2"); // VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x16, 0xca]); //
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0x0a], "vmovhps xmm1, xmm0, qword [rdx]"); // VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x0a], "vmovhps qword [rdx], xmm1"); // VMOVHPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0xca], "vmovaps ymm1{k5}{z}, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0x0a], "vmovaps ymm1{k5}{z}, ymmword [rdx]"); // VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xbd, 0x28, 0x0a]); // no broadcast
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0xca], "vmovaps ymm1, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0xca], "vmovaps ymm1{k5}, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0x0a], "vmovaps ymm1, ymmword [rdx]"); // VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
@@ -207,6 +211,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0x0a], "vmovaps zmmword [rdx], zmm1"); // VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0x0a], "vmovaps zmmword [rdx]{k5}, zmm1"); // VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x29, 0xca], "vmovaps xmm2{k5}{z}, xmm1"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x9d, 0x29, 0xca]); // no sae/er support on movaps
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0xca], "vmovaps xmm2, xmm1"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0xca], "vmovaps xmm2{k5}, xmm1"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0x0a], "vmovaps xmmword [rdx], xmm1"); // VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
@@ -214,13 +219,20 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2b, 0x0a], "vmovntps ymmword [rdx], ymm1"); // VMOVNTPS_MEMf32_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x2b, 0x0a], "vmovntps zmmword [rdx], zmm1"); // VMOVNTPS_MEMf32_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x2b, 0x0a], "vmovntps xmmword [rdx], xmm1"); // VMOVNTPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x38, 0x2b, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xa8, 0x2b, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x28, 0x2b, 0x0a]); // no W=1
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2e, 0xca], "vucomiss xmm1{sae}, xmm2"); // VUCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0xca], "vucomiss xmm1, xmm2"); // VUCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0x0a], "vucomiss xmm1, dword [rdx]"); // VUCOMISS_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x2e, 0x0a]); // no broadcast from memory
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x68, 0x2e, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x2e, 0x0a]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2f, 0xca], "vcomiss xmm1{sae}, xmm2"); // VCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0xca], "vcomiss xmm1, xmm2"); // VCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x0a], "vcomiss xmm1, dword [rdx]"); // VCOMISS_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rz-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfc, 0xfd, 0x51, 0xca]); // requires W=0
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x51, 0xca], "vsqrtps zmm1{rz-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x51, 0xca], "vsqrtps zmm1{k5}{rz-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rd-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
@@ -447,6 +459,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0x0a], "vmulps xmm1{k5}, xmm0, xmmword [rdx]"); // VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{z}{sae}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5a, 0xca], "vcvtps2pd zmm1{sae}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x78, 0x5a, 0xca]); // W=0
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{sae}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}{z}, dword [rdx]{1to4}"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5a, 0x0a], "vcvtps2pd ymm1, dword [rdx]{1to4}"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
@@ -832,6 +845,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0xc2, 0xca, 0xcc], "vcmpps k1{sae}, zmm0, zmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}{sae}, zmm0, zmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc2, 0x0a, 0xcc], "vcmpps k1, ymm0, dword [rdx]{1to8}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xb8, 0xc2, 0x0a, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0xca, 0xcc], "vcmpps k1, ymm0, ymm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, ymm0, ymm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -851,6 +865,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc6, 0x0a, 0xcc], "vshufps ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0xca, 0xcc]); // no broadcast from register source
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0xca, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -888,6 +903,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0x0a], "vmovupd ymm1{k5}, ymmword [rdx]"); // VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0xca], "vmovupd zmm1{k5}{z}, zmm2"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0x0a], "vmovupd zmm1{k5}{z}, zmmword [rdx]"); // VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xdd, 0x10, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0xca], "vmovupd zmm1, zmm2"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0xca], "vmovupd zmm1{k5}, zmm2"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0x0a], "vmovupd zmm1, zmmword [rdx]"); // VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -919,6 +935,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x14, 0x0a], "vunpcklpd ymm1, ymm0, qword [rdx]{1to4}"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x14, 0x0a], "vunpcklpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0xca], "vunpcklpd ymm1{k5}{z}, ymm0, ymm2"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0xca]); // no broadcast in reg-reg
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0x0a], "vunpcklpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0xca], "vunpcklpd ymm1, ymm0, ymm2"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0xca], "vunpcklpd ymm1{k5}, ymm0, ymm2"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
@@ -946,6 +963,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x15, 0x0a], "vunpckhpd ymm1, ymm0, qword [rdx]{1to4}"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x15, 0x0a], "vunpckhpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0xca], "vunpckhpd ymm1{k5}{z}, ymm0, ymm2"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0xca]); // no broadcast in reg-reg
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0x0a], "vunpckhpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0xca], "vunpckhpd ymm1, ymm0, ymm2"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0xca], "vunpckhpd ymm1{k5}, ymm0, ymm2"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
@@ -976,6 +994,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0xca], "vmovapd ymm1, ymm2"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0xca], "vmovapd ymm1{k5}, ymm2"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0x0a], "vmovapd ymm1, ymmword [rdx]"); // VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0x28, 0x0a]); // no broadcast
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0x0a], "vmovapd ymm1{k5}, ymmword [rdx]"); // VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0xca], "vmovapd zmm1{k5}{z}, zmm2"); // VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0x0a], "vmovapd zmm1{k5}{z}, zmmword [rdx]"); // VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -1007,9 +1026,16 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2b, 0x0a], "vmovntpd ymmword [rdx], ymm1"); // VMOVNTPD_MEMf64_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x2b, 0x0a], "vmovntpd zmmword [rdx], zmm1"); // VMOVNTPD_MEMf64_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x2b, 0x0a], "vmovntpd xmmword [rdx], xmm1"); // VMOVNTPD_MEMf64_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2b, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2b, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x08, 0x2b, 0x0a]); // no W=-
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2e, 0xca], "vucomisd xmm1{sae}, xmm2"); // VUCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x79, 0x2e, 0xca]); // mask reg must be 000
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0xca], "vucomisd xmm1, xmm2"); // VUCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0x0a], "vucomisd xmm1, qword [rdx]"); // VUCOMISD_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2e, 0x0a]); // no broadcast from memory
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x68, 0x2e, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2e, 0x0a]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2f, 0xca], "vcomisd xmm1{sae}, xmm2"); // VCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0xca], "vcomisd xmm1, xmm2"); // VCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0x0a], "vcomisd xmm1, qword [rdx]"); // VCOMISD_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
@@ -1289,6 +1315,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0xca], "vcvtps2dq ymm1{k5}{z}, ymm2"); // VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}{z}, ymmword [rdx]"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0xca], "vcvtps2dq ymm1, ymm2"); // VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x28, 0x5b, 0xca]); // no W=1
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0xca], "vcvtps2dq ymm1{k5}, ymm2"); // VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0x0a], "vcvtps2dq ymm1, ymmword [rdx]"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}, ymmword [rdx]"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
@@ -1563,6 +1590,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, dword [rdx]{1to8}"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0xca], "vpcmpgtd k1, ymm0, ymm2"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0xca], "vpcmpgtd k1{k5}, ymm0, ymm2"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0xca]); // no broadcast on reg operand (no sae)
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0x0a], "vpcmpgtd k1, ymm0, ymmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, ymmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x66, 0x0a], "vpcmpgtd k1, zmm0, dword [rdx]{1to16}"); // VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX
@@ -1740,8 +1768,10 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0x0a], "vpunpckhqdq xmm1, xmm0, xmmword [rdx]"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0xca], "vmovq xmm1, rdx"); // VMOVQ_XMMu64_GPR64u64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x6e, 0xca]); //no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0x0a], "vmovq xmm1, qword [rdx]"); // VMOVQ_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6e, 0xca], "vmovd xmm1, edx"); // VMOVD_XMMu32_GPR32u32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x6e, 0xca]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6e, 0x0a], "vmovd xmm1, dword [rdx]"); // VMOVD_XMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0xca], "vmovdqa64 ymm1{k5}{z}, ymm2"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0x0a], "vmovdqa64 ymm1{k5}{z}, ymmword [rdx]"); // VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX
@@ -2182,6 +2212,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0xca], "vmovq rdx, xmm1"); // VMOVQ_GPR64u64_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0x0a], "vmovq qword [rdx], xmm1"); // VMOVQ_MEMu64_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7e, 0xca], "vmovd edx, xmm1"); // VMOVD_GPR32u32_XMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x7e, 0xca]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7e, 0x0a], "vmovd dword [rdx], xmm1"); // VMOVD_MEMu32_XMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7f, 0xca], "vmovdqa64 ymm2{k5}{z}, ymm1"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0xca], "vmovdqa64 ymm2, ymm1"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
@@ -2217,6 +2248,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}{sae}, zmm0, zmm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, qword [rdx]{1to4}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0xc2, 0x0a, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0xca, 0xcc], "vcmppd k1, ymm0, ymm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, ymm0, ymm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, ymmword [rdx], 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
@@ -2708,6 +2740,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0x0a], "vpmulhw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{z}{sae}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0xe6, 0xca], "vcvttpd2dq ymm1{sae}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x78, 0xe6, 0xca]); // requires W=1
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{sae}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, qword [rdx]{1to4}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xe6, 0x0a], "vcvttpd2dq xmm1, qword [rdx]{1to4}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX
@@ -2739,6 +2772,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0x0a], "vmovntdq ymmword [rdx], ymm1"); // VMOVNTDQ_MEMu32_YMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe7, 0x0a], "vmovntdq zmmword [rdx], zmm1"); // VMOVNTDQ_MEMu32_ZMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe7, 0x0a], "vmovntdq xmmword [rdx], xmm1"); // VMOVNTDQ_MEMu32_XMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0xca]); // no reg-reg encoding
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0xca], "vpsubsb ymm1{k5}{z}, ymm0, ymm2"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0x0a], "vpsubsb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0xca], "vpsubsb ymm1, ymm0, ymm2"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX
@@ -3056,6 +3090,8 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0x0a], "vpmaddwd xmm1{k5}, xmm0, xmmword [rdx]"); // VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0xca], "vpsadbw ymm1, ymm0, ymm2"); // VPSADBW_YMMu16_YMMu8_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0x0a], "vpsadbw ymm1, ymm0, ymmword [rdx]"); // VPSADBW_YMMu16_YMMu8_MEMu8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0xf6, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xa8, 0xf6, 0x0a]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0xca], "vpsadbw zmm1, zmm0, zmm2"); // VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0x0a], "vpsadbw zmm1, zmm0, zmmword [rdx]"); // VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0xca], "vpsadbw xmm1, xmm0, xmm2"); // VPSADBW_XMMu16_XMMu8_XMMu8_AVX512, extension: AVX512EVEX
@@ -3218,16 +3254,21 @@ fn tests_66_0f() {
 fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0xca], "vmovss xmm1{k5}{z}, xmm0, xmm2"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0x0a], "vmovss xmm1{k5}{z}, dword [rdx]"); // VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6f, 0x10, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0xca], "vmovss xmm1, xmm0, xmm2"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0xca], "vmovss xmm1{k5}, xmm0, xmm2"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0x0a], "vmovss xmm1, dword [rdx]"); // VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x10, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0x0a], "vmovss xmm1{k5}, dword [rdx]"); // VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0xca], "vmovss xmm2{k5}{z}, xmm0, xmm1"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0xca], "vmovss xmm2, xmm0, xmm1"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0xca], "vmovss xmm2{k5}, xmm0, xmm1"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x3d, 0x11, 0xca]);
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0x0a], "vmovss dword [rdx], xmm1"); // VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0x0a], "vmovss dword [rdx]{k5}, xmm1"); // VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0xca], "vmovsldup ymm1{k5}{z}, ymm2"); // VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0x0a], "vmovsldup ymm1{k5}{z}, ymmword [rdx]"); // VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0xca], "vmovsldup ymm1, ymm2"); // VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0xca], "vmovsldup ymm1{k5}, ymm2"); // VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
@@ -3266,7 +3307,10 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2a, 0xca], "vcvtsi2ss xmm1{rz-sae}, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0xca], "vcvtsi2ss xmm1{rd-sae}, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2a, 0xca]); // mask reg must be 000
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0x0a], "vcvtsi2ss xmm1, xmm0, qword [rdx]"); // VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2a, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2a, 0xca], "vcvtsi2ss xmm1{rz-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x2a, 0xca], "vcvtsi2ss xmm1{rd-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
@@ -3277,14 +3321,21 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x2a, 0xca], "vcvtsi2ss xmm1{rne-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2c, 0xca], "vcvttss2si rcx{sae}, xmm2"); // VCVTTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0xca], "vcvttss2si rcx, xmm2"); // VCVTTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2c, 0xca]); // mask register must be 000
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0x0a], "vcvttss2si rcx, dword [rdx]"); // VCVTTSS2SI_GPR64i64_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2c, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x2c, 0x0a]); // no broadcast, regardless of W
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2c, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2c, 0xca], "vcvttss2si ecx{sae}, xmm2"); // VCVTTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); // VCVTTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2c, 0x0a], "vcvttss2si ecx, dword [rdx]"); // VCVTTSS2SI_GPR32i32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2d, 0xca], "vcvtss2si rcx{rz-sae}, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0xca], "vcvtss2si rcx{rd-sae}, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0xca], "vcvtss2si rcx, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2d, 0xca]); // mask register must be 000
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0x0a], "vcvtss2si rcx, dword [rdx]"); // VCVTSS2SI_GPR64i64_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2d, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2d, 0xca], "vcvtss2si ecx{rz-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x2d, 0xca], "vcvtss2si ecx{rd-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2d, 0xca], "vcvtss2si ecx, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
@@ -3349,6 +3400,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x59, 0xca], "vmulss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0xca], "vcvtss2sd xmm1{sae}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0x0a]); // no broadcast with memory source
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{sae}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0x0a], "vcvtss2sd xmm1{k5}{z}, xmm0, dword [rdx]"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -3582,6 +3634,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x7b, 0xca], "vcvtusi2ss xmm1{rd-sae}, xmm0, rdx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0xca], "vcvtusi2ss xmm1, xmm0, rdx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0x0a], "vcvtusi2ss xmm1, xmm0, qword [rdx]"); // VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x7b, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x7b, 0xca], "vcvtusi2ss xmm1{rz-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x7b, 0xca], "vcvtusi2ss xmm1{rd-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7b, 0xca], "vcvtusi2ss xmm1, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
@@ -3591,6 +3644,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x7b, 0xca], "vcvtusi2ss xmm1{ru-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x7b, 0xca], "vcvtusi2ss xmm1{rne-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0xca], "vmovq xmm1, xmm2"); // VMOVQ_XMMu64_XMMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x88, 0x7e, 0xca]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0x0a], "vmovq xmm1, qword [rdx]"); // VMOVQ_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x7f, 0xca], "vmovdqu64 ymm2{k5}{z}, ymm1"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0xca], "vmovdqu64 ymm2, ymm1"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
@@ -3626,6 +3680,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}{sae}, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0xca, 0xcc], "vcmpss k1, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0xc2, 0xca, 0xcc]); // do not allow L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0x0a, 0xcc], "vcmpss k1, xmm0, dword [rdx], 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpss k1{k5}, xmm0, dword [rdx], 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0xfd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
@@ -3699,6 +3754,8 @@ fn tests_f2_0f() {
 fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0xca], "vmovsd xmm1{k5}{z}, xmm0, xmm2"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0x0a], "vmovsd xmm1{k5}{z}, qword [rdx]"); // VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x10, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0xca], "vmovsd xmm1, xmm0, xmm2"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0xca], "vmovsd xmm1{k5}, xmm0, xmm2"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0x0a], "vmovsd xmm1, qword [rdx]"); // VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -3706,10 +3763,13 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0xca], "vmovsd xmm2{k5}{z}, xmm0, xmm1"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0xca], "vmovsd xmm2, xmm0, xmm1"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0xca], "vmovsd xmm2{k5}, xmm0, xmm1"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x3d, 0x11, 0xca]);
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0x0a], "vmovsd qword [rdx], xmm1"); // VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0x0a], "vmovsd qword [rdx]{k5}, xmm1"); // VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0xca], "vmovddup ymm1{k5}{z}, ymm2"); // VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0x0a], "vmovddup ymm1{k5}{z}, ymmword [rdx]"); // VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x12, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0xca], "vmovddup ymm1, ymm2"); // VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0xca], "vmovddup ymm1{k5}, ymm2"); // VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0x0a], "vmovddup ymm1, ymmword [rdx]"); // VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -3763,6 +3823,8 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0xca], "vsqrtsd xmm1, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0xca], "vsqrtsd xmm1{k5}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0x0a], "vsqrtsd xmm1, xmm0, qword [rdx]"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x38, 0x51, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x51, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0x0a], "vsqrtsd xmm1{k5}, xmm0, qword [rdx]"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x51, 0xca], "vsqrtsd xmm1{ru-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
@@ -3814,6 +3876,8 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0x0a], "vcvtsd2ss xmm1{k5}{z}, xmm0, qword [rdx]"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x5a, 0x0a]); // no L'L=11 unless for sae
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x5a, 0x0a]); // no L'L=11 unless for sae
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0xca], "vcvtsd2ss xmm1, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0x0a], "vcvtsd2ss xmm1, xmm0, qword [rdx]"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
@@ -3871,6 +3935,7 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x5e, 0xca], "vdivsd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5f, 0xca], "vmaxsd xmm1{sae}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7f, 0x78, 0x5f, 0xca]); // requires W=1
     test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5f, 0xca], "vmaxsd xmm1{k5}{sae}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0x0a], "vmaxsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
@@ -4032,6 +4097,7 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x7b, 0xca], "vcvtusi2sd xmm1{rd-sae}, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0xca], "vcvtusi2sd xmm1, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0x0a], "vcvtusi2sd xmm1, xmm0, qword [rdx]"); // VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x7b, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x7b, 0xca], "vcvtusi2sd xmm1, xmm0, edx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7b, 0x0a], "vcvtusi2sd xmm1, xmm0, dword [rdx]"); // VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x7b, 0xca], "vcvtusi2sd xmm1{ru-sae}, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX
@@ -4072,6 +4138,7 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0xca, 0xcc], "vcmpsd k1{k5}, xmm0, xmm2, 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0x0a, 0xcc], "vcmpsd k1, xmm0, qword [rdx], 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpsd k1{k5}, xmm0, qword [rdx], 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0xc2, 0x0a, 0xcc]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rz-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0xe6, 0xca], "vcvtpd2dq ymm1{rz-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rz-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
@@ -4278,6 +4345,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0x0a], "vpsllvw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x13, 0xca], "vcvtph2ps zmm1{k5}{z}{sae}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x13, 0xca], "vcvtph2ps zmm1{sae}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x78, 0x13, 0x0a]); // W=0
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x13, 0xca], "vcvtph2ps zmm1{k5}{sae}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0xca], "vcvtph2ps ymm1{k5}{z}, xmm2"); // VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0x0a], "vcvtph2ps ymm1{k5}{z}, xmmword [rdx]"); // VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX
@@ -4310,6 +4378,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x14, 0x0a], "vprorvd ymm1, ymm0, dword [rdx]{1to8}"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x14, 0x0a], "vprorvd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0xca], "vprorvd ymm1{k5}{z}, ymm0, ymm2"); // VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0xca]); // no broadcast
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0x0a], "vprorvd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0xca], "vprorvd ymm1, ymm0, ymm2"); // VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0xca], "vprorvd ymm1{k5}, ymm0, ymm2"); // VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
@@ -4682,12 +4751,14 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0x0a], "vpmovsxwq xmm1, dword [rdx]"); // VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0x0a], "vpmovsxwq xmm1{k5}, dword [rdx]"); // VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0xca], "vpmovsxdq ymm1{k5}{z}, xmm2"); // VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x25, 0xca]); // W must be 1
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0x0a], "vpmovsxdq ymm1{k5}{z}, xmmword [rdx]"); // VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0xca], "vpmovsxdq ymm1, xmm2"); // VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0xca], "vpmovsxdq ymm1{k5}, xmm2"); // VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0x0a], "vpmovsxdq ymm1, xmmword [rdx]"); // VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0x0a], "vpmovsxdq ymm1{k5}, xmmword [rdx]"); // VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0xca], "vpmovsxdq zmm1{k5}{z}, ymm2"); // VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xcd, 0x25, 0xca]);
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0x0a], "vpmovsxdq zmm1{k5}{z}, ymmword [rdx]"); // VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0xca], "vpmovsxdq zmm1, ymm2"); // VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0xca], "vpmovsxdq zmm1{k5}, ymm2"); // VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX
@@ -4703,10 +4774,12 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0xca], "vptestmw k1{k5}, ymm0, ymm2"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0x0a], "vptestmw k1, ymm0, ymmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0x0a], "vptestmw k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x26, 0x0a]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0xca], "vptestmb k1, ymm0, ymm2"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0xca], "vptestmb k1{k5}, ymm0, ymm2"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0x0a], "vptestmb k1, ymm0, ymmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0x0a], "vptestmb k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x26, 0x0a]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0xca], "vptestmw k1, zmm0, zmm2"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0xca], "vptestmw k1{k5}, zmm0, zmm2"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0x0a], "vptestmw k1, zmm0, zmmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX
@@ -4731,12 +4804,15 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0x0a], "vptestmq k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x27, 0x0a], "vptestmd k1, ymm0, dword [rdx]{1to8}"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, dword [rdx]{1to8}"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xdd, 0x27, 0x0a]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0xca], "vptestmd k1, ymm0, ymm2"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0xca], "vptestmd k1{k5}, ymm0, ymm2"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0xca]); // no invalid broadcast mode
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0x0a], "vptestmd k1, ymm0, ymmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x27, 0x0a], "vptestmq k1, zmm0, qword [rdx]{1to8}"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x27, 0x0a], "vptestmq k1{k5}, zmm0, qword [rdx]{1to8}"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xdd, 0x27, 0x0a]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x27, 0x0a], "vptestmq k1, xmm0, qword [rdx]{1to2}"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x27, 0x0a], "vptestmq k1{k5}, xmm0, qword [rdx]{1to2}"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0xca], "vptestmq k1, zmm0, zmm2"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX
@@ -4763,6 +4839,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x28, 0x0a], "vpmuldq ymm1, ymm0, qword [rdx]{1to4}"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x28, 0x0a], "vpmuldq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0xca], "vpmuldq ymm1{k5}{z}, ymm0, ymm2"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0xca]); // no broadcast on register source
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0x0a], "vpmuldq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0xca], "vpmuldq ymm1, ymm0, ymm2"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0xca], "vpmuldq ymm1{k5}, ymm0, ymm2"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
@@ -4790,6 +4867,8 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, qword [rdx]{1to4}"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0xca], "vpcmpeqq k1, ymm0, ymm2"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0xca], "vpcmpeqq k1{k5}, ymm0, ymm2"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x29, 0xca]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0xca]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0x0a], "vpcmpeqq k1, ymm0, ymmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, ymmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x29, 0x0a], "vpcmpeqq k1, zmm0, qword [rdx]{1to8}"); // VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX
@@ -4805,6 +4884,8 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0x0a], "vpcmpeqq k1, xmm0, xmmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0x0a], "vpcmpeqq k1{k5}, xmm0, xmmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0x0a], "vmovntdqa ymm1, ymmword [rdx]"); // VMOVNTDQA_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0xca]); // no register source
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xa8, 0x2a, 0x0a]); // no broadcast
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x0a], "vmovntdqa zmm1, zmmword [rdx]"); // VMOVNTDQA_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x0a], "vmovntdqa xmm1, xmmword [rdx]"); // VMOVNTDQA_XMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2b, 0x0a], "vpackusdw ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
@@ -4925,6 +5006,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0x0a], "vscalefsd xmm1, xmm0, qword [rdx]"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0x0a], "vscalefsd xmm1{k5}, xmm0, qword [rdx]"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0x0a]); // sae is indicated by evex.b, with memory source evex.b implies broadcast as well. vscalefss does not broadcast, so reject.
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x2d, 0xca], "vscalefss xmm1{rz-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x2d, 0xca], "vscalefss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
@@ -5526,6 +5608,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x43, 0xca], "vgetexpss xmm1{k5}{sae}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0xca], "vgetexpss xmm1{k5}{z}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0x0a], "vgetexpss xmm1{k5}{z}, xmm0, dword [rdx]"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x43, 0x0a]); // no broadcast
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0xca], "vgetexpss xmm1, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0xca], "vgetexpss xmm1{k5}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0x0a], "vgetexpss xmm1, xmm0, dword [rdx]"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -5810,6 +5893,8 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0x0a], "vrcp14ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0xca], "vrcp14ss xmm1, xmm0, xmm2"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0xca], "vrcp14ss xmm1{k5}, xmm0, xmm2"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4d, 0xca]); // no sae
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x6d, 0x4d, 0xca]); // no L'L=11
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0x0a], "vrcp14ss xmm1, xmm0, dword [rdx]"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0x0a], "vrcp14ss xmm1{k5}, xmm0, dword [rdx]"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}{z}, qword [rdx]{1to4}"); // VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -5828,6 +5913,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}{z}, ymmword [rdx]"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0xca], "vrsqrt14ps ymm1, ymm2"); // VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0xca], "vrsqrt14ps ymm1{k5}, ymm2"); // VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0xca]); // no sae
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0x0a], "vrsqrt14ps ymm1, ymmword [rdx]"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}, ymmword [rdx]"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}{z}, qword [rdx]{1to8}"); // VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -5875,6 +5961,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}{z}, xmm0, xmm2"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0xca], "vrsqrt14ss xmm1, xmm0, xmm2"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x68, 0x4f, 0xca]); // no L'L=11
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}, xmm0, xmm2"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0x0a], "vrsqrt14ss xmm1, xmm0, dword [rdx]"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}, xmm0, dword [rdx]"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -6194,6 +6281,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0xca], "vpcompressb ymm2{k5}, ymm1"); // VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0x0a], "vpcompressb ymmword [rdx], ymm1"); // VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0x0a], "vpcompressb ymmword [rdx]{k5}, ymm1"); // VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x63, 0x0a]); // no zero-merge on memory operands
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x63, 0xca], "vpcompressw zmm2{k5}{z}, zmm1"); // VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0xca], "vpcompressw zmm2, zmm1"); // VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0xca], "vpcompressw zmm2{k5}, zmm1"); // VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
@@ -6649,6 +6737,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0xca], "vpbroadcastb ymm1{k5}{z}, xmm2"); // VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0x0a], "vpbroadcastb ymm1{k5}{z}, byte [rdx]"); // VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0xca], "vpbroadcastb ymm1, xmm2"); // VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x78, 0xca]); // deny evex.b
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0xca], "vpbroadcastb ymm1{k5}, xmm2"); // VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0x0a], "vpbroadcastb ymm1, byte [rdx]"); // VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0x0a], "vpbroadcastb ymm1{k5}, byte [rdx]"); // VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX
@@ -6684,6 +6773,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0x0a], "vpbroadcastw xmm1{k5}, word [rdx]"); // VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7a, 0xca], "vpbroadcastb ymm1{k5}{z}, edx"); // VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7a, 0xca], "vpbroadcastb ymm1, edx"); // VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7a, 0xca]); // still no evex.b
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7a, 0xca], "vpbroadcastb ymm1{k5}, edx"); // VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7a, 0xca], "vpbroadcastb zmm1{k5}{z}, edx"); // VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7a, 0xca], "vpbroadcastb zmm1, edx"); // VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
@@ -6705,6 +6795,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7c, 0xca], "vpbroadcastq ymm1{k5}, rdx"); // VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7c, 0xca], "vpbroadcastd ymm1{k5}{z}, edx"); // VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7c, 0xca], "vpbroadcastd ymm1, edx"); // VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7c, 0xca]); // no broadcast here either
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7c, 0xca], "vpbroadcastd ymm1{k5}, edx"); // VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7c, 0xca], "vpbroadcastq zmm1{k5}{z}, rdx"); // VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7c, 0xca], "vpbroadcastq zmm1, rdx"); // VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX
@@ -7324,6 +7415,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0x0a], "vfmadd132ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_avx_full(&[0x62, 0xf2, 0x7d, 0x68, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); // no L'L==0 when not sae
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0xca], "vfmadd132ss xmm1{k5}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0x0a], "vfmadd132ss xmm1, xmm0, dword [rdx]"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0x0a], "vfmadd132ss xmm1{k5}, xmm0, dword [rdx]"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -9141,6 +9233,8 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0x0a], "vgf2p8mulb xmm1{k5}, xmm0, xmmword [rdx]"); // VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0xca], "vaesenc ymm1, ymm0, ymm2"); // VAESENC_YMMu128_YMMu128_YMMu128_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0x0a], "vaesenc ymm1, ymm0, ymmword [rdx]"); // VAESENC_YMMu128_YMMu128_MEMu128_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x38, 0xdc, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xa8, 0xdc, 0x0a]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0xca], "vaesenc zmm1, zmm0, zmm2"); // VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0x0a], "vaesenc zmm1, zmm0, zmmword [rdx]"); // VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0xca], "vaesenc xmm1, xmm0, xmm2"); // VAESENC_XMMu128_XMMu128_XMMu128_AVX512, extension: AVX512EVEX
@@ -9171,6 +9265,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0xca], "vpmovuswb xmm2{k5}, ymm1"); // VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0x0a], "vpmovuswb xmmword [rdx], ymm1"); // VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0x0a], "vpmovuswb xmmword [rdx]{k5}, ymm1"); // VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xad, 0x10, 0x0a]); // cannot set evex.z on stores.
     test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x10, 0xca], "vpmovuswb ymm2{k5}{z}, zmm1"); // VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0xca], "vpmovuswb ymm2, zmm1"); // VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0xca], "vpmovuswb ymm2{k5}, zmm1"); // VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
@@ -9206,6 +9301,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0xca], "vpmovusqb xmm2{k5}, zmm1"); // VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0x0a], "vpmovusqb qword [rdx], zmm1"); // VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0x0a], "vpmovusqb qword [rdx]{k5}, zmm1"); // VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xcd, 0x12, 0x0a]);
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, xmm1"); // VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0xca], "vpmovusqb xmm2, xmm1"); // VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0xca], "vpmovusqb xmm2{k5}, xmm1"); // VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX
@@ -9412,6 +9508,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x28, 0xca], "vpmovm2w xmm1, k2"); // VPMOVM2W_XMMu16_MASKmskw_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x28, 0xca], "vpmovm2b zmm1, k2"); // VPMOVM2B_ZMMu8_MASKmskw_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x28, 0xca], "vpmovm2b xmm1, k2"); // VPMOVM2B_XMMu8_MASKmskw_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x28, 0xca]); //
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x29, 0xca], "vpmovw2m k1, ymm2"); // VPMOVW2M_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x29, 0xca], "vpmovb2m k1, ymm2"); // VPMOVB2M_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x29, 0xca], "vpmovw2m k1, zmm2"); // VPMOVW2M_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
@@ -9519,6 +9616,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x38, 0xca], "vpmovm2d xmm1, k2"); // VPMOVM2D_XMMu32_MASKmskw_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x39, 0xca], "vpmovq2m k1, ymm2"); // VPMOVQ2M_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x39, 0xca], "vpmovd2m k1, ymm2"); // VPMOVD2M_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xa8, 0x39, 0xca]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x39, 0xca], "vpmovq2m k1, zmm2"); // VPMOVQ2M_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x39, 0xca], "vpmovq2m k1, xmm2"); // VPMOVQ2M_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x39, 0xca], "vpmovd2m k1, zmm2"); // VPMOVD2M_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX
@@ -9526,6 +9624,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x3a, 0xca], "vpbroadcastmw2d ymm1, k2"); // VPBROADCASTMW2D_YMMu32_MASKu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x3a, 0xca], "vpbroadcastmw2d zmm1, k2"); // VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x3a, 0xca], "vpbroadcastmw2d xmm1, k2"); // VPBROADCASTMW2D_XMMu32_MASKu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x3a, 0xca]); // no zero "mask merge", no masking at all
     test_avx_full(&[0x62, 0xf2, 0x7e, 0xbd, 0x52, 0x0a], "vdpbf16ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x52, 0x0a], "vdpbf16ps ymm1, ymm0, dword [rdx]{1to8}"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x52, 0x0a], "vdpbf16ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
@@ -9557,6 +9656,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x72, 0x0a], "vcvtneps2bf16 xmm1, dword [rdx]{1to8}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, dword [rdx]{1to8}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}{z}, ymm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0xca]); // no register-register broadcast
     test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, ymmword [rdx]"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0xca], "vcvtneps2bf16 xmm1, ymm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}, ymm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
@@ -9585,6 +9685,8 @@ fn tests_f2_0f38() {
 fn tests_f3_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0x0a], "vp2intersectd k1, xmm0, xmmword [rdx]"); // VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); // VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX
+    test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); // VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7f, 0x09, 0x68, 0xca]); // requires mask reg to be 000
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1, xmm0, xmmword [rdx]"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0xca], "vcvtne2ps2bf16 xmm1, xmm0, xmm2"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmmword [rdx]"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX
@@ -9639,6 +9741,7 @@ fn tests_f3_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7f, 0xdd, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0x0a], "vp2intersectq k1, xmm0, xmmword [rdx]"); // VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0xca], "vp2intersectq k1, xmm0, xmm2"); // VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xff, 0x09, 0x68, 0xca]); // requires mask reg to be 000
     test_avx_full(&[0x62, 0xf2, 0xff, 0x18, 0x68, 0x0a], "vp2intersectq k1, xmm0, qword [rdx]{1to2}"); // VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0x0a], "vp2intersectq k1, ymm0, ymmword [rdx]"); // VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0xca], "vp2intersectq k1, ymm0, ymm2"); // VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX
@@ -9653,6 +9756,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x00, 0x0a, 0xcc], "vpermq ymm1, qword [rdx]{1to4}, 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}, qword [rdx]{1to4}, 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}{z}, ymm2, 0xcc"); // VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0xca, 0xcc]); // no broadcast on reg-reg ops
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0xca, 0xcc], "vpermq ymm1, ymm2, 0xcc"); // VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}, ymm2, 0xcc"); // VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX
@@ -9743,6 +9847,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x04, 0x0a, 0xcc], "vpermilps ymm1, dword [rdx]{1to8}, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}, dword [rdx]{1to8}, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}{z}, ymm2, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0xca, 0xcc]); // no broadcast on reg sources
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0xca, 0xcc], "vpermilps ymm1, ymm2, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}, ymm2, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -9858,6 +9963,8 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, dword [rdx], 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x5d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0xca, 0xcc], "vrndscaless xmm1, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1, xmm0, dword [rdx], 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -9866,16 +9973,21 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xa8, 0x0b, 0xca, 0xcc]); // no zero-merge without mask reg
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, qword [rdx], 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1, xmm0, qword [rdx], 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0b, 0x0a, 0xcc]); // no broadcast on memory source
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x68, 0x0b, 0x0a, 0xcc]); // L'L==11 requires sae
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}, xmm0, qword [rdx], 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0xca, 0xcc], "vpalignr ymm1, ymm0, ymm2, 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}, ymm0, ymm2, 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x3d, 0x0f, 0xca, 0xcc]); // no broadcast
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0x0a, 0xcc], "vpalignr ymm1, ymm0, ymmword [rdx], 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0f, 0x0a, 0xcc]); // still no broadcast
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0xca, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0x0a, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
@@ -9890,14 +10002,22 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0x0a, 0xcc], "vpalignr xmm1, xmm0, xmmword [rdx], 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0x0a, 0xcc], "vpalignr xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0xca, 0xcc], "vpextrb edx, xmm1, 0xcc"); // VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x14, 0xca, 0xcc]); // no zero mask-merge, no masking!
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x14, 0xca, 0xcc]); // no broadcast
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0x0a, 0xcc], "vpextrb byte [rdx], xmm1, 0xcc"); // VPEXTRB_MEMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0xca, 0xcc], "vpextrw edx, xmm1, 0xcc"); // VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x15, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x15, 0xca, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0x0a, 0xcc], "vpextrw word [rdx], xmm1, 0xcc"); // VPEXTRW_MEMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0xca, 0xcc], "vpextrq rdx, xmm1, 0xcc"); // VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0x0a, 0xcc], "vpextrq qword [rdx], xmm1, 0xcc"); // VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x16, 0xca, 0xcc], "vpextrd edx, xmm1, 0xcc"); // VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x16, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x16, 0xca, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x16, 0x0a, 0xcc], "vpextrd dword [rdx], xmm1, 0xcc"); // VPEXTRD_MEMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0xca, 0xcc], "vextractps edx, xmm1, 0xcc"); // VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x17, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x17, 0xca, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0x0a, 0xcc], "vextractps dword [rdx], xmm1, 0xcc"); // VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmmword [rdx], 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
@@ -9933,6 +10053,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}, ymm1, 0xcc"); // VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [rdx], ymm1, 0xcc"); // VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [rdx]{k5}, ymm1, 0xcc"); // VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x19, 0x0a, 0xcc]); // no zero-merge with memmory dest
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2, zmm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}, zmm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
@@ -9965,6 +10086,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2{k5}, zmm1, 0xcc"); // VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [rdx], zmm1, 0xcc"); // VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xcd, 0x1b, 0x0a, 0xcc]); // no zero-merge into memory
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}{sae}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{sae}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{sae}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -9973,7 +10095,9 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}, ymm1, 0xcc"); // VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [rdx], ymm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [rdx]{k5}, ymm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x1d, 0x0a, 0xcc]); // no zero-merge into memory
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x1d, 0x0a, 0xcc]); // no L'L==11 for non-sae
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0x0a, 0xcc], "vcvtps2ph ymmword [rdx], zmm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -10056,10 +10180,16 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0x0a, 0xcc], "vpcmpd k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0xca, 0xcc], "vpinsrb xmm1, xmm0, edx, 0xcc"); // VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x20, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x20, 0xca, 0xcc]); //
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0x0a, 0xcc], "vpinsrb xmm1, xmm0, byte [rdx], 0xcc"); // VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0xca, 0xcc], "vinsertps xmm1, xmm0, xmm2, 0xcc"); // VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x21, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x21, 0xca, 0xcc]); //
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0x0a, 0xcc], "vinsertps xmm1, xmm0, dword [rdx], 0xcc"); // VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0xca, 0xcc], "vpinsrq xmm1, xmm0, rdx, 0xcc"); // VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x22, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x22, 0xca, 0xcc]); //
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0x0a, 0xcc], "vpinsrq xmm1, xmm0, qword [rdx], 0xcc"); // VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x22, 0xca, 0xcc], "vpinsrd xmm1, xmm0, edx, 0xcc"); // VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x22, 0x0a, 0xcc], "vpinsrd xmm1, xmm0, dword [rdx], 0xcc"); // VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX
@@ -10303,6 +10433,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0xca, 0xcc], "vpcmpub k1, ymm0, ymm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xad, 0x3e, 0xca, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0x0a, 0xcc], "vpcmpub k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0xca, 0xcc], "vpcmpuw k1, zmm0, zmm2, 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX
@@ -10350,6 +10481,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1, ymm0, ymm2, 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymm2, 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1, ymm0, ymmword [rdx], 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x38, 0x42, 0x0a, 0xcc]); // no broadcast
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
@@ -10400,11 +10532,14 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1, zmm0, zmmword [rdx], 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0xca, 0xcc], "vpclmulqdq ymm1, ymm0, ymm2, 0xcc"); // VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x29, 0x44, 0xca, 0xcc]); // mask reg must be 000
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0x0a, 0xcc], "vpclmulqdq ymm1, ymm0, ymmword [rdx], 0xcc"); // VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0xca, 0xcc], "vpclmulqdq zmm1, zmm0, zmm2, 0xcc"); // VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0x0a, 0xcc], "vpclmulqdq zmm1, zmm0, zmmword [rdx], 0xcc"); // VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0xca, 0xcc], "vpclmulqdq xmm1, xmm0, xmm2, 0xcc"); // VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0x0a, 0xcc], "vpclmulqdq xmm1, xmm0, xmmword [rdx], 0xcc"); // VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x44, 0x0a, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x44, 0x0a, 0xcc]); //
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x50, 0xca, 0xcc], "vrangepd zmm1{sae}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
@@ -10641,6 +10776,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0x0a, 0xcc], "vreducess xmm1{k5}, xmm0, dword [rdx], 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [rdx]{1to4}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [rdx]{1to4}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x66, 0x0a, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0xca, 0xcc], "vfpclasspd k1, ymm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, ymm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0x0a, 0xcc], "vfpclasspd k1, ymmword [rdx], 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX
diff --git a/test/protected_mode/evex_generated.rs b/test/protected_mode/evex_generated.rs
index 9c3a06e..bd553d5 100644
--- a/test/protected_mode/evex_generated.rs
+++ b/test/protected_mode/evex_generated.rs
@@ -133,7 +133,9 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x0a], "vmovups xmmword [edx]{k5}, xmm1");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0x4a, 0x01], "vmovups xmmword [edx + 0x10], xmm1");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x4a, 0x01], "vmovups xmmword [edx + 0x10]{k5}, xmm1");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0xca], "vmovhlps xmm1, xmm0, xmm2");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x12, 0xca]); // no broadcast
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x0a], "vmovlps xmm1, xmm0, qword [edx]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x4a, 0x01], "vmovlps xmm1, xmm0, qword [edx + 0x8]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x13, 0x0a], "vmovlps qword [edx], xmm1");
@@ -229,12 +231,14 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0x4a, 0x01], "vunpckhps xmm1, xmm0, xmmword [edx + 0x10]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0x4a, 0x01], "vunpckhps xmm1{k5}, xmm0, xmmword [edx + 0x10]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0xca], "vmovlhps xmm1, xmm0, xmm2");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x16, 0xca]); //
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0x0a], "vmovhps xmm1, xmm0, qword [edx]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0x4a, 0x01], "vmovhps xmm1, xmm0, qword [edx + 0x8]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x0a], "vmovhps qword [edx], xmm1");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x4a, 0x01], "vmovhps qword [edx + 0x8], xmm1");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0xca], "vmovaps ymm1{k5}{z}, ymm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0x0a], "vmovaps ymm1{k5}{z}, ymmword [edx]");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xbd, 0x28, 0x0a]); // no broadcast
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0x4a, 0x01], "vmovaps ymm1{k5}{z}, ymmword [edx + 0x20]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0xca], "vmovaps ymm1, ymm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0xca], "vmovaps ymm1{k5}, ymm2");
@@ -253,6 +257,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x28, 0x4a, 0x01], "vmovaps zmm1{k5}, zmmword [edx + 0x40]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0xca], "vmovaps xmm1{k5}{z}, xmm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0x0a], "vmovaps xmm1{k5}{z}, xmmword [edx]");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x9d, 0x29, 0xca]); // no sae/er support on movaps
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0x4a, 0x01], "vmovaps xmm1{k5}{z}, xmmword [edx + 0x10]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x28, 0xca], "vmovaps xmm1, xmm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x28, 0xca], "vmovaps xmm1{k5}, xmm2");
@@ -287,15 +292,22 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x2b, 0x4a, 0x01], "vmovntps zmmword [edx + 0x40], zmm1");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x2b, 0x0a], "vmovntps xmmword [edx], xmm1");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x2b, 0x4a, 0x01], "vmovntps xmmword [edx + 0x10], xmm1");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x38, 0x2b, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xa8, 0x2b, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x28, 0x2b, 0x0a]); // no W=1
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2e, 0xca], "vucomiss xmm1{sae}, xmm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0xca], "vucomiss xmm1, xmm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0x0a], "vucomiss xmm1, dword [edx]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0x4a, 0x01], "vucomiss xmm1, dword [edx + 0x4]");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x2e, 0x0a]); // no broadcast from memory
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x68, 0x2e, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x2e, 0x0a]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2f, 0xca], "vcomiss xmm1{sae}, xmm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0xca], "vcomiss xmm1, xmm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x0a], "vcomiss xmm1, dword [edx]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x4a, 0x01], "vcomiss xmm1, dword [edx + 0x4]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rz-sae}, zmm2");
+    test_invalid(&[0x62, 0xf1, 0xfc, 0xfd, 0x51, 0xca]); // requires W=0
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x51, 0xca], "vsqrtps zmm1{rz-sae}, zmm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x51, 0xca], "vsqrtps zmm1{k5}{rz-sae}, zmm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rd-sae}, zmm2");
@@ -648,6 +660,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0x4a, 0x01], "vmulps xmm1{k5}, xmm0, xmmword [edx + 0x10]");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{z}{sae}, ymm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5a, 0xca], "vcvtps2pd zmm1{sae}, ymm2");
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x78, 0x5a, 0xca]); // W=0
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{sae}, ymm2");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}{z}, dword [edx]{1to4}");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1{k5}{z}, dword [edx + 0x4]{1to4}");
@@ -1231,6 +1244,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0xc2, 0xca, 0xcc], "vcmpps k1{sae}, zmm0, zmm2, 0xcc");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}{sae}, zmm0, zmm2, 0xcc");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc2, 0x0a, 0xcc], "vcmpps k1, ymm0, dword [edx]{1to8}, 0xcc");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xb8, 0xc2, 0x0a, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, ymm0, dword [edx]{1to8}, 0xcc");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, ymm0, dword [edx + 0x4]{1to8}, 0xcc");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc");
@@ -1262,6 +1276,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0xca, 0xcc]); // no broadcast from register source
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc6, 0x0a, 0xcc], "vshufps ymm1, ymm0, dword [edx]{1to8}, 0xcc");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc");
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc");
@@ -16383,4 +16398,140 @@ fn tests_f3_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0xab, 0x0a], "v4fnmaddss xmm1{k5}, xmm0, xmmword [edx]");
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0xab, 0x4a, 0x01], "v4fnmaddss xmm1, xmm0, xmmword [edx + 0x10]");
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0xab, 0x4a, 0x01], "v4fnmaddss xmm1{k5}, xmm0, xmmword [edx + 0x10]");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x12, 0xca]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x16, 0xca]); //
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xbd, 0x28, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x9d, 0x29, 0xca]); // no sae/er support on movaps
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x38, 0x2b, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xa8, 0x2b, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x28, 0x2b, 0x0a]); // no W=1
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x2e, 0x0a]); // no broadcast from memory
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x68, 0x2e, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x2e, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0xfc, 0xfd, 0x51, 0xca]); // requires W=0
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x78, 0x5a, 0xca]); // W=0
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xb8, 0xc2, 0x0a, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0xca, 0xcc]); // no broadcast from register source
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xdd, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0xca]); // no broadcast in reg-reg
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0xca]); // no broadcast in reg-reg
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0x28, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2b, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2b, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x08, 0x2b, 0x0a]); // no W=-
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x79, 0x2e, 0xca]); // mask reg must be 000
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2e, 0x0a]); // no broadcast from memory
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x68, 0x2e, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2e, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x28, 0x5b, 0xca]); // no W=1
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0xca]); // no broadcast on reg operand (no sae)
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x6e, 0xca]); //no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x6e, 0xca]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x7e, 0xca]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0xc2, 0x0a, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x78, 0xe6, 0xca]); // requires W=1
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0xca]); // no reg-reg encoding
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0xf6, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xa8, 0xf6, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6f, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x3d, 0x11, 0xca]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2a, 0xca]); // mask reg must be 000
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2a, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2c, 0xca]); // mask register must be 000
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2c, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x2c, 0x0a]); // no broadcast, regardless of W
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2c, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2d, 0xca]); // mask register must be 000
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2d, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0x0a]); // no broadcast with memory source
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x7b, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x88, 0x7e, 0xca]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0xc2, 0xca, 0xcc]); // do not allow L'L=11
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0x3d, 0x11, 0xca]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x12, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0x38, 0x51, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x51, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x5a, 0x0a]); // no L'L=11 unless for sae
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x5a, 0x0a]); // no L'L=11 unless for sae
+    test_invalid(&[0x62, 0xf1, 0x7f, 0x78, 0x5f, 0xca]); // requires W=1
+    test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x7b, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0xc2, 0x0a, 0xcc]); // no L'L=11
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x78, 0x13, 0x0a]); // W=0
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0xca]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x25, 0xca]); // W must be 1
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xcd, 0x25, 0xca]);
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x26, 0x0a]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x26, 0x0a]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xdd, 0x27, 0x0a]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0xca]); // no invalid broadcast mode
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xdd, 0x27, 0x0a]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0xca]); // no broadcast on register source
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x29, 0xca]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0xca]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0xca]); // no register source
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xa8, 0x2a, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0x0a]); // sae is indicated by evex.b, with memory source evex.b implies broadcast as well. vscalefss does not broadcast, so reject.
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x43, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4d, 0xca]); // no sae
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x6d, 0x4d, 0xca]); // no L'L=11
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0xca]); // no sae
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x68, 0x4f, 0xca]); // no L'L=11
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x63, 0x0a]); // no zero-merge on memory operands
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x78, 0xca]); // deny evex.b
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7a, 0xca]); // still no evex.b
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7c, 0xca]); // no broadcast here either
+    test_avx_full(&[0x62, 0xf2, 0x7d, 0x68, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); // no L'L==0 when not sae
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x38, 0xdc, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xa8, 0xdc, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xad, 0x10, 0x0a]); // cannot set evex.z on stores.
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xcd, 0x12, 0x0a]);
+    test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x28, 0xca]); //
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xa8, 0x39, 0xca]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x3a, 0xca]); // no zero "mask merge", no masking at all
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0xca]); // no register-register broadcast
+    test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); // VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7f, 0x09, 0x68, 0xca]); // requires mask reg to be 000
+    test_invalid(&[0x62, 0xf2, 0xff, 0x09, 0x68, 0xca]); // requires mask reg to be 000
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0xca, 0xcc]); // no broadcast on reg-reg ops
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0xca, 0xcc]); // no broadcast on reg sources
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x5d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xa8, 0x0b, 0xca, 0xcc]); // no zero-merge without mask reg
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0b, 0x0a, 0xcc]); // no broadcast on memory source
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x68, 0x0b, 0x0a, 0xcc]); // L'L==11 requires sae
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x3d, 0x0f, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0f, 0x0a, 0xcc]); // still no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x14, 0xca, 0xcc]); // no zero mask-merge, no masking!
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x14, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x15, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x15, 0xca, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x16, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x16, 0xca, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x17, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x17, 0xca, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x19, 0x0a, 0xcc]); // no zero-merge with memmory dest
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xcd, 0x1b, 0x0a, 0xcc]); // no zero-merge into memory
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x1d, 0x0a, 0xcc]); // no zero-merge into memory
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x1d, 0x0a, 0xcc]); // no L'L==11 for non-sae
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x20, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x20, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x21, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x21, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x22, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x22, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xad, 0x3e, 0xca, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x38, 0x42, 0x0a, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x29, 0x44, 0xca, 0xcc]); // mask reg must be 000
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x44, 0x0a, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x44, 0x0a, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x66, 0x0a, 0xcc]); // no zero mask-merge
 }
diff --git a/test/real_mode/mod.rs b/test/real_mode/mod.rs
index af5a315..b8a636c 100644
--- a/test/real_mode/mod.rs
+++ b/test/real_mode/mod.rs
@@ -16712,6 +16712,142 @@ fn test_real_mode() {
     test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc");
     test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{z}{sae}, zmm2, 0xcc");
     test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc");
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x12, 0xca]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x16, 0xca]); //
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xbd, 0x28, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x9d, 0x29, 0xca]); // no sae/er support on movaps
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x38, 0x2b, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xa8, 0x2b, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x28, 0x2b, 0x0a]); // no W=1
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x2e, 0x0a]); // no broadcast from memory
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x68, 0x2e, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x2e, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0xfc, 0xfd, 0x51, 0xca]); // requires W=0
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x78, 0x5a, 0xca]); // W=0
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xb8, 0xc2, 0x0a, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0xca, 0xcc]); // no broadcast from register source
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xdd, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0xca]); // no broadcast in reg-reg
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0xca]); // no broadcast in reg-reg
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0x28, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2b, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2b, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x08, 0x2b, 0x0a]); // no W=-
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x79, 0x2e, 0xca]); // mask reg must be 000
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2e, 0x0a]); // no broadcast from memory
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x68, 0x2e, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2e, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x28, 0x5b, 0xca]); // no W=1
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0xca]); // no broadcast on reg operand (no sae)
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x6e, 0xca]); //no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x6e, 0xca]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x7e, 0xca]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0xc2, 0x0a, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x78, 0xe6, 0xca]); // requires W=1
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0xca]); // no reg-reg encoding
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0xf6, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xa8, 0xf6, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6f, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x3d, 0x11, 0xca]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2a, 0xca]); // mask reg must be 000
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2a, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2c, 0xca]); // mask register must be 000
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2c, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x2c, 0x0a]); // no broadcast, regardless of W
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2c, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2d, 0xca]); // mask register must be 000
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2d, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0x0a]); // no broadcast with memory source
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x7b, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x88, 0x7e, 0xca]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0xc2, 0xca, 0xcc]); // do not allow L'L=11
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0x3d, 0x11, 0xca]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x12, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0x38, 0x51, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x51, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x5a, 0x0a]); // no L'L=11 unless for sae
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x5a, 0x0a]); // no L'L=11 unless for sae
+    test_invalid(&[0x62, 0xf1, 0x7f, 0x78, 0x5f, 0xca]); // requires W=1
+    test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x7b, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0xc2, 0x0a, 0xcc]); // no L'L=11
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x78, 0x13, 0x0a]); // W=0
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0xca]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x25, 0xca]); // W must be 1
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xcd, 0x25, 0xca]);
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x26, 0x0a]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x26, 0x0a]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xdd, 0x27, 0x0a]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0xca]); // no invalid broadcast mode
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xdd, 0x27, 0x0a]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0xca]); // no broadcast on register source
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x29, 0xca]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0xca]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0xca]); // no register source
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xa8, 0x2a, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0x0a]); // sae is indicated by evex.b, with memory source evex.b implies broadcast as well. vscalefss does not broadcast, so reject.
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x43, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4d, 0xca]); // no sae
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x6d, 0x4d, 0xca]); // no L'L=11
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0xca]); // no sae
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x68, 0x4f, 0xca]); // no L'L=11
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x63, 0x0a]); // no zero-merge on memory operands
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x78, 0xca]); // deny evex.b
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7a, 0xca]); // still no evex.b
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7c, 0xca]); // no broadcast here either
+    test_display(&[0x62, 0xf2, 0x7d, 0x68, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); // no L'L==0 when not sae
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x38, 0xdc, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xa8, 0xdc, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xad, 0x10, 0x0a]); // cannot set evex.z on stores.
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xcd, 0x12, 0x0a]);
+    test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x28, 0xca]); //
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xa8, 0x39, 0xca]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x3a, 0xca]); // no zero "mask merge", no masking at all
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0xca]); // no register-register broadcast
+    test_display(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); // VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7f, 0x09, 0x68, 0xca]); // requires mask reg to be 000
+    test_invalid(&[0x62, 0xf2, 0xff, 0x09, 0x68, 0xca]); // requires mask reg to be 000
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0xca, 0xcc]); // no broadcast on reg-reg ops
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0xca, 0xcc]); // no broadcast on reg sources
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x5d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xa8, 0x0b, 0xca, 0xcc]); // no zero-merge without mask reg
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0b, 0x0a, 0xcc]); // no broadcast on memory source
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x68, 0x0b, 0x0a, 0xcc]); // L'L==11 requires sae
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x3d, 0x0f, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0f, 0x0a, 0xcc]); // still no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x14, 0xca, 0xcc]); // no zero mask-merge, no masking!
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x14, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x15, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x15, 0xca, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x16, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x16, 0xca, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x17, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x17, 0xca, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x19, 0x0a, 0xcc]); // no zero-merge with memmory dest
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xcd, 0x1b, 0x0a, 0xcc]); // no zero-merge into memory
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x1d, 0x0a, 0xcc]); // no zero-merge into memory
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x1d, 0x0a, 0xcc]); // no L'L==11 for non-sae
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x20, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x20, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x21, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x21, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x22, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x22, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xad, 0x3e, 0xca, 0xcc]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x38, 0x42, 0x0a, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x29, 0x44, 0xca, 0xcc]); // mask reg must be 000
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x44, 0x0a, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x44, 0x0a, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x66, 0x0a, 0xcc]); // no zero mask-merge
     test_display(&[0x63, 0xc1], "arpl cx, ax");
     test_display(&[0x65, 0x66, 0x0f, 0x01, 0xdc], "stgi");
     test_display(&[0x65, 0x66, 0x66, 0x64, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword fs:[bx]");
author	iximeow <me@iximeow.net>	2026-05-08 01:19:33 +0000
committer	iximeow <me@iximeow.net>	2026-05-25 01:43:55 +0000
commit	f900cfe558b97d187226c6e0791ad8992ba8f4a0 (patch)
tree	8909e645eed396945cba92e9e1a370579d9ce26a
parent	307d39dedfabaa0a0400ba62cd9a418d3f94a582 (diff)