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author | iximeow <me@iximeow.net> | 2023-07-24 06:41:02 -0700 |
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committer | iximeow <me@iximeow.net> | 2023-07-24 06:41:02 -0700 |
commit | ab51fd1b2c7cf1b7bb6f84c5b07e06245f6b3d99 (patch) | |
tree | 80b2a81dfb805c49a5c3a43296835bd5195e422a /CHANGELOG | |
parent | 855fa08f1d2f4bc405a1cfc205b5e9321dd4ebf5 (diff) |
fix handling of lar/lsl source register
Diffstat (limited to 'CHANGELOG')
-rw-r--r-- | CHANGELOG | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -25,6 +25,11 @@ encodings and bitness * in some cases, instructions loading a single-precision float reported 8-byte loads * in some cases, instructions loading a double-precision float reported 4-byte loads +* fix register sizes for lar/lsl + * 16 bits are read from the source register, but x86 docs state that the + source register is written as 16-bit, 32-bit, or 64-bit, as prefixes dictate. + memory is always written as `word [addr]`, which was correct before and + remains the case. ## 1.1.5 * fix several typos across crate docs - thank you Bruce! (aka github user waywardmonkeys) |