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authoriximeow <me@iximeow.net>2023-02-05 15:30:51 -0800
committeriximeow <me@iximeow.net>2023-07-04 19:01:38 -0700
commit1130f9f3270be56f2dd77361c34412a43e2b795e (patch)
tree602c94d1af52098b320094031f679cdfea1c2bb8 /src/long_mode/vex.rs
parentf17450483ef9dc18d2b97e6287063a572c7e898c (diff)
more micro-opts...
set_embedded_instructions was unnecessarily appilied to many operand codes; this was never a correctness issue, but meant many operand decodings took a few more instruction than necessary to do nothing. setting all registers to `rax` is unnecessary, only the first register's defaulting to `rax` is effectual. this allows for not using a movabs to load initial rax state. adjust vex decoder inlining. this will be followed up by some cleanup for vex operand codes.
Diffstat (limited to 'src/long_mode/vex.rs')
-rw-r--r--src/long_mode/vex.rs3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index 31f9e11..24ff2a8 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -102,7 +102,7 @@ enum VEXOperandCode {
MXCSR,
}
-#[inline(never)]
+#[inline(always)]
pub(crate) fn three_byte_vex<
T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpeax_arch::Arch>::Word>,
S: DescriptionSink<FieldDescription>,
@@ -224,6 +224,7 @@ pub(crate) fn three_byte_vex<
read_vex_instruction(m, words, instruction, p, sink)
}
+#[inline(always)]
pub(crate) fn two_byte_vex<
T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpeax_arch::Arch>::Word>,
S: DescriptionSink<FieldDescription>,