update yaxpeax-x86 to yaxpeax-arch 0.1.0 interfaces

1 files changed, 139 insertions, 143 deletions

diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index 31297f7..a3bdd6d 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -1,3 +1,6 @@
+use yaxpeax_arch::Reader;
+
+use crate::long_mode::Arch;
 use crate::long_mode::OperandSpec;
 use crate::long_mode::DecodeError;
 use crate::long_mode::RegSpec;
@@ -97,10 +100,9 @@ enum VEXOperandCode {
 }
 
 #[inline(never)]
-pub(crate) fn three_byte_vex<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Instruction, mut length: u8) -> Result<(), DecodeError> {
-    let vex_byte_one = bytes.next().ok_or(DecodeError::ExhaustedInput)?;
-    let vex_byte_two = bytes.next().ok_or(DecodeError::ExhaustedInput)?;
-    length += 2;
+pub(crate) fn three_byte_vex<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpeax_arch::Arch>::Word>>(words: &mut T, instruction: &mut Instruction) -> Result<(), DecodeError> {
+    let vex_byte_one = words.next().ok().ok_or(DecodeError::ExhaustedInput)?;
+    let vex_byte_two = words.next().ok().ok_or(DecodeError::ExhaustedInput)?;
     let p = vex_byte_two & 0x03;
     let p = match p {
         0x00 => VEXOpcodePrefix::None,
@@ -125,14 +127,11 @@ pub(crate) fn three_byte_vex<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &
     };
     instruction.prefixes.vex_from_c4(vex_byte_one, vex_byte_two);
 
-    read_vex_instruction(m, bytes, instruction, &mut length, p)?;
-    instruction.length = length;
-    Ok(())
+    read_vex_instruction(m, words, instruction, p)
 }
 
-pub(crate) fn two_byte_vex<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Instruction, mut length: u8) -> Result<(), DecodeError> {
-    let vex_byte = bytes.next().ok_or(DecodeError::ExhaustedInput)?;
-    length += 1;
+pub(crate) fn two_byte_vex<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpeax_arch::Arch>::Word>>(words: &mut T, instruction: &mut Instruction) -> Result<(), DecodeError> {
+    let vex_byte = words.next().ok().ok_or(DecodeError::ExhaustedInput)?;
     let p = vex_byte & 0x03;
     let p = match p {
         0x00 => VEXOpcodePrefix::None,
@@ -147,16 +146,14 @@ pub(crate) fn two_byte_vex<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mu
     };
     instruction.prefixes.vex_from_c5(vex_byte);
 
-    read_vex_instruction(VEXOpcodeMap::Map0F, bytes, instruction, &mut length, p)?;
-    instruction.length = length;
-    Ok(())
+    read_vex_instruction(VEXOpcodeMap::Map0F, words, instruction, p)
 }
 
-fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Instruction, length: &mut u8, operand_code: VEXOperandCode) -> Result<(), DecodeError> {
+fn read_vex_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpeax_arch::Arch>::Word>>(words: &mut T, instruction: &mut Instruction, operand_code: VEXOperandCode) -> Result<(), DecodeError> {
 //    println!("operand code: {:?}", operand_code);
     match operand_code {
         VEXOperandCode::VPS_71 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 != 0xc0 {
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
@@ -180,13 +177,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.vex_reg.bank = RegisterBank::X;
             instruction.operands[0] = OperandSpec::RegVex;
             instruction.operands[1] = OperandSpec::RegRRR;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmI8;
             instruction.operand_count = 3;
             Ok(())
         }
         VEXOperandCode::VPS_71_L => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 != 0xc0 {
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
@@ -213,13 +210,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.vex_reg.bank = RegisterBank::Y;
             instruction.operands[0] = OperandSpec::RegVex;
             instruction.operands[1] = OperandSpec::RegRRR;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmI8;
             instruction.operand_count = 3;
             Ok(())
         }
         VEXOperandCode::VPS_72 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 != 0xc0 {
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
@@ -243,13 +240,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.vex_reg.bank = RegisterBank::X;
             instruction.operands[0] = OperandSpec::RegVex;
             instruction.operands[1] = OperandSpec::RegRRR;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmI8;
             instruction.operand_count = 3;
             Ok(())
         }
         VEXOperandCode::VPS_72_L => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 != 0xc0 {
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
@@ -273,13 +270,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.vex_reg.bank = RegisterBank::Y;
             instruction.operands[0] = OperandSpec::RegVex;
             instruction.operands[1] = OperandSpec::RegRRR;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmI8;
             instruction.operand_count = 3;
             Ok(())
         }
         VEXOperandCode::VPS_73 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 != 0xc0 {
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
@@ -306,13 +303,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.vex_reg.bank = RegisterBank::X;
             instruction.operands[0] = OperandSpec::RegVex;
             instruction.operands[1] = OperandSpec::RegRRR;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmI8;
             instruction.operand_count = 3;
             Ok(())
         }
         VEXOperandCode::VPS_73_L => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 != 0xc0 {
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
@@ -345,17 +342,17 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.vex_reg.bank = RegisterBank::Y;
             instruction.operands[0] = OperandSpec::RegVex;
             instruction.operands[1] = OperandSpec::RegRRR;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmI8;
             instruction.operand_count = 3;
             Ok(())
         }
         VEXOperandCode::VMOVSS_10 |
         VEXOperandCode::VMOVSD_10 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             match mem_oper {
                 OperandSpec::RegMMM => {
@@ -381,10 +378,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
         },
         VEXOperandCode::VMOVSS_11 |
         VEXOperandCode::VMOVSD_11 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[2] = OperandSpec::RegRRR;
             match mem_oper {
                 OperandSpec::RegMMM => {
@@ -410,7 +407,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         },
         VEXOperandCode::VMOVLPS_12 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.opcode = if modrm & 0xc0 == 0xc0 {
                 Opcode::VMOVHLPS
             } else {
@@ -421,12 +418,12 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
-            instruction.operands[2] = read_E_xmm(bytes, instruction, modrm, length)?;
+            instruction.operands[2] = read_E_xmm(words, instruction, modrm)?;
             instruction.operand_count = 3;
             Ok(())
         }
         VEXOperandCode::VMOVHPS_16 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.opcode = if modrm & 0xc0 == 0xc0 {
                 Opcode::VMOVLHPS
             } else {
@@ -437,7 +434,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
-            instruction.operands[2] = read_E_xmm(bytes, instruction, modrm, length)?;
+            instruction.operands[2] = read_E_xmm(words, instruction, modrm)?;
             instruction.operand_count = 3;
             Ok(())
         }
@@ -450,10 +447,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 4)?;
             instruction.operands[0] = mem_oper;
             instruction.operands[1] = OperandSpec::RegRRR;
             instruction.operands[2] = OperandSpec::ImmU8;
@@ -477,7 +474,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.modrm_mmm.bank = RegisterBank::Q;
             }
             instruction.operand_count = 3;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             Ok(())
         },
         VEXOperandCode::G_xmm_Eq => {
@@ -485,10 +482,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E(bytes, instruction, modrm, 8, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 8)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
             if mem_oper != OperandSpec::RegMMM {
@@ -502,10 +499,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 4)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
             if mem_oper != OperandSpec::RegMMM {
@@ -519,10 +516,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E(bytes, instruction, modrm, 8, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 8)?;
             instruction.operands[0] = mem_oper;
             instruction.operands[1] = OperandSpec::RegRRR;
             if mem_oper != OperandSpec::RegMMM {
@@ -536,10 +533,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 4)?;
             instruction.operands[0] = mem_oper;
             instruction.operands[1] = OperandSpec::RegRRR;
             if mem_oper != OperandSpec::RegMMM {
@@ -553,10 +550,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::D);
-            let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 4)?;
             if let OperandSpec::RegMMM = mem_oper {
                 instruction.modrm_mmm.bank = RegisterBank::X;
             } else {
@@ -572,10 +569,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Q);
-            let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 4)?;
             if let OperandSpec::RegMMM = mem_oper {
                 instruction.modrm_mmm.bank = RegisterBank::X;
             } else {
@@ -596,10 +593,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             match (op, mem_oper) {
                 (VEXOperandCode::E_G_xmm, OperandSpec::RegMMM) => {
                     /* this is the only accepted operand */
@@ -629,10 +626,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::D);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             if mem_oper != OperandSpec::RegMMM {
                 return Err(DecodeError::InvalidOperand);
             }
@@ -646,10 +643,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::D);
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             if mem_oper != OperandSpec::RegMMM {
                 return Err(DecodeError::InvalidOperand);
             }
@@ -663,16 +660,16 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::D);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             if mem_oper != OperandSpec::RegMMM {
                 return Err(DecodeError::InvalidOperand);
             }
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmU8;
             instruction.operand_count = 3;
             Ok(())
@@ -682,13 +679,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = mem_oper;
             instruction.operands[1] = OperandSpec::RegRRR;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmU8;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = 16;
@@ -701,13 +698,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = mem_oper;
             instruction.operands[1] = OperandSpec::RegRRR;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmU8;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = 16;
@@ -721,10 +718,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::D);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             if mem_oper != OperandSpec::RegMMM {
                 return Err(DecodeError::InvalidOperand);
             }
@@ -738,10 +735,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::D);
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             if mem_oper != OperandSpec::RegMMM {
                 return Err(DecodeError::InvalidOperand);
             }
@@ -758,7 +755,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             match (op, modrm & 0xc0) {
                 (VEXOperandCode::G_U_xmm, 0xc0) => {
                     /* this is the only accepted operand */
@@ -774,7 +771,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             }
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
             if mem_oper != OperandSpec::RegMMM {
@@ -794,10 +791,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
             if mem_oper != OperandSpec::RegMMM {
@@ -811,10 +808,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
             if mem_oper != OperandSpec::RegMMM {
@@ -829,7 +826,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 == 0xc0 {
                 if let VEXOperandCode::G_ymm_M_xmm = op {
                     return Err(DecodeError::InvalidOperand);
@@ -837,7 +834,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             }
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
             if mem_oper != OperandSpec::RegMMM {
@@ -857,10 +854,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
             if mem_oper != OperandSpec::RegMMM {
@@ -876,7 +873,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             match (op, modrm & 0xc0) {
                 (VEXOperandCode::M_G_ymm, 0xc0) => {
                     return Err(DecodeError::InvalidOperand);
@@ -888,7 +885,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             }
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.operands[0] = mem_oper;
             instruction.operands[1] = OperandSpec::RegRRR;
             if mem_oper != OperandSpec::RegMMM {
@@ -904,7 +901,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                 instruction.opcode = Opcode::Invalid;
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             match (op, modrm & 0xc0) {
                 (VEXOperandCode::G_M_ymm, 0xc0) => {
                     return Err(DecodeError::InvalidOperand);
@@ -916,7 +913,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             }
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
             if mem_oper != OperandSpec::RegMMM {
@@ -927,7 +924,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
         }
         op @ VEXOperandCode::G_V_E_ymm |
         op @ VEXOperandCode::G_V_M_ymm => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if let VEXOperandCode::G_V_M_ymm = op {
                 if modrm & 0xc0 == 0xc0 {
                     return Err(DecodeError::InvalidOperand);
@@ -936,7 +933,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
             instruction.vex_reg.bank = RegisterBank::Y;
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
@@ -947,15 +944,15 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_E_ymm_imm8 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
             instruction.vex_reg.bank = RegisterBank::Y;
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[3] = OperandSpec::ImmU8;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = 32;
@@ -964,14 +961,14 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::M_V_G_ymm => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 == 0xc0 {
                 return Err(DecodeError::InvalidOperand);
             }
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
             instruction.vex_reg.bank = RegisterBank::Y;
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.operands[0] = mem_oper;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = OperandSpec::RegRRR;
@@ -982,13 +979,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_M_xmm => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 == 0xc0 {
                 return Err(DecodeError::InvalidOperand);
             }
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
@@ -1003,10 +1000,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_E_xmm => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
@@ -1023,10 +1020,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_xmm_Ed => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 4)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
@@ -1037,10 +1034,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_xmm_Eq => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E(bytes, instruction, modrm, 8, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 8)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
@@ -1051,14 +1048,14 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_E_xmm_imm8 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[3] = OperandSpec::ImmU8;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = 16;
@@ -1067,15 +1064,15 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
             instruction.vex_reg.bank = RegisterBank::Y;
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[3] = OperandSpec::ImmU8;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = 16;
@@ -1084,14 +1081,14 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::M_V_G_xmm => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             if modrm & 0xc0 == 0xc0 {
                 return Err(DecodeError::InvalidOperand);
             }
 
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = mem_oper;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = OperandSpec::RegRRR;
@@ -1103,10 +1100,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
         }
 
         VEXOperandCode::G_Ex_V_xmm => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.sib_index.bank = RegisterBank::X;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
@@ -1118,10 +1115,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_Ey_V_xmm => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.vex_reg.bank = RegisterBank::X;
             instruction.sib_index.bank = RegisterBank::Y;
             instruction.operands[0] = OperandSpec::RegRRR;
@@ -1134,10 +1131,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_Ey_V_ymm => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.vex_reg.bank = RegisterBank::Y;
             instruction.sib_index.bank = RegisterBank::Y;
             instruction.operands[0] = OperandSpec::RegRRR;
@@ -1154,7 +1151,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_E => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             let (opwidth, bank) = if instruction.prefixes.vex().w() {
                 (8, RegisterBank::Q)
             } else {
@@ -1163,7 +1160,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), bank);
             instruction.vex_reg.bank = bank;
-            let mem_oper = read_E(bytes, instruction, modrm, opwidth, length)?;
+            let mem_oper = read_E(words, instruction, modrm, opwidth)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
@@ -1174,7 +1171,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_E_V => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             let (opwidth, bank) = if instruction.prefixes.vex().w() {
                 (8, RegisterBank::Q)
             } else {
@@ -1183,7 +1180,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), bank);
             instruction.vex_reg.bank = bank;
-            let mem_oper = read_E(bytes, instruction, modrm, opwidth, length)?;
+            let mem_oper = read_E(words, instruction, modrm, opwidth)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
             instruction.operands[2] = OperandSpec::RegVex;
@@ -1194,7 +1191,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_E_Ib => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             let (opwidth, bank) = if instruction.prefixes.vex().w() {
                 (8, RegisterBank::Q)
             } else {
@@ -1202,10 +1199,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             };
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), bank);
-            let mem_oper = read_E(bytes, instruction, modrm, opwidth, length)?;
+            let mem_oper = read_E(words, instruction, modrm, opwidth)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmI8;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = opwidth;
@@ -1214,7 +1211,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::BMI1_F3 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.opcode = match (modrm >> 3) & 7 {
                 1 => {
                     Opcode::BLSR
@@ -1237,7 +1234,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             };
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), bank);
-            let mem_oper = read_E(bytes, instruction, modrm, opwidth, length)?;
+            let mem_oper = read_E(words, instruction, modrm, opwidth)?;
             instruction.operands[0] = OperandSpec::RegVex;
             instruction.operands[1] = mem_oper;
             instruction.operand_count = 2;
@@ -1248,7 +1245,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::MXCSR => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.opcode = match (modrm >> 3) & 7 {
                 2 => {
                     Opcode::VLDMXCSR
@@ -1261,7 +1258,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
                     return Err(DecodeError::InvalidOpcode);
                 }
             };
-            let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 4)?;
             if let OperandSpec::RegMMM = mem_oper {
                 return Err(DecodeError::InvalidOperand);
             }
@@ -1276,13 +1273,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             if instruction.vex_reg.num != 0 {
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmU8;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = 16;
@@ -1294,13 +1291,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             if instruction.vex_reg.num != 0 {
                 return Err(DecodeError::InvalidOperand);
             }
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[2] = OperandSpec::ImmU8;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = 32;
@@ -1309,15 +1306,15 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_E_ymm_ymm4 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), RegisterBank::Y);
             instruction.vex_reg.bank = RegisterBank::Y;
-            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_ymm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)? >> 4;
+            instruction.imm = read_imm_unsigned(words, 1)? >> 4;
             instruction.operands[3] = OperandSpec::Reg4;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = 32;
@@ -1326,15 +1323,15 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_E_xmm_xmm4 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), RegisterBank::X);
             instruction.vex_reg.bank = RegisterBank::X;
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)? >> 4;
+            instruction.imm = read_imm_unsigned(words, 1)? >> 4;
             instruction.operands[3] = OperandSpec::Reg4;
             if mem_oper != OperandSpec::RegMMM {
                 instruction.mem_size = 16;
@@ -1343,11 +1340,11 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_ymm_E_xmm => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), RegisterBank::Y);
             instruction.vex_reg.bank = RegisterBank::Y;
-            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            let mem_oper = read_E_xmm(words, instruction, modrm)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
@@ -1358,16 +1355,16 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             Ok(())
         }
         VEXOperandCode::G_V_xmm_Ev_imm8 => {
-            let modrm = read_modrm(bytes, length)?;
+            let modrm = read_modrm(words)?;
             instruction.modrm_rrr =
                 RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), RegisterBank::X);
             instruction.vex_reg.bank = RegisterBank::X;
             // TODO: but the memory access is word-sized
-            let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
+            let mem_oper = read_E(words, instruction, modrm, 4)?;
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operands[1] = OperandSpec::RegVex;
             instruction.operands[2] = mem_oper;
-            instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+            instruction.imm = read_imm_unsigned(words, 1)?;
             instruction.operands[3] = OperandSpec::ImmI8;
             if mem_oper != OperandSpec::RegMMM {
                 match instruction.opcode {
@@ -1395,9 +1392,8 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
     }
 }
 
-fn read_vex_instruction<T: Iterator<Item=u8>>(opcode_map: VEXOpcodeMap, bytes: &mut T, instruction: &mut Instruction, length: &mut u8, p: VEXOpcodePrefix) -> Result<(), DecodeError> {
-    let opc = bytes.next().ok_or(DecodeError::ExhaustedInput)?;
-    *length += 1;
+fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpeax_arch::Arch>::Word>>(opcode_map: VEXOpcodeMap, words: &mut T, instruction: &mut Instruction, p: VEXOpcodePrefix) -> Result<(), DecodeError> {
+    let opc = words.next().ok().ok_or(DecodeError::ExhaustedInput)?;
 
     // the name of this bit is `L` in the documentation, so use the same name here.
     #[allow(non_snake_case)]
@@ -3437,5 +3433,5 @@ fn read_vex_instruction<T: Iterator<Item=u8>>(opcode_map: VEXOpcodeMap, bytes: &
         }
     };
     instruction.opcode = opcode;
-    read_vex_operands(bytes, instruction, length, operand_code)
+    read_vex_operands(words, instruction, operand_code)
 }