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authoriximeow <me@iximeow.net>2021-07-04 12:20:13 -0700
committeriximeow <me@iximeow.net>2021-07-04 12:36:03 -0700
commit48559b18574b44e2de879a5c641ab602ec22f0d8 (patch)
tree0195cd249c1ce2429b12a14d063447fe96e3283e /src/long_mode/vex.rs
parent404cb6e81988ed84a75c89d67bf324409e22a390 (diff)
fix several incorrect tests and docs in 64- and 32-bit modes
Diffstat (limited to 'src/long_mode/vex.rs')
-rw-r--r--src/long_mode/vex.rs10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index 67c4965..5695b17 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -411,7 +411,7 @@ fn read_vex_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
instruction.opcode = if modrm & 0xc0 == 0xc0 {
Opcode::VMOVHLPS
} else {
- instruction.mem_size = 4;
+ instruction.mem_size = 8;
Opcode::VMOVLPS
};
instruction.regs[0] =
@@ -1925,7 +1925,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
} else {
VEXOperandCode::G_V_E_xmm
}),
- 0xDA => (Opcode::VPMINSW, if L {
+ 0xDA => (Opcode::VPMINUB, if L {
VEXOperandCode::G_V_E_ymm
} else {
VEXOperandCode::G_V_E_xmm
@@ -3201,12 +3201,12 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
VEXOperandCode::G_E_xmm_imm8
}),
0x0A => (Opcode::VROUNDSS, if L {
- VEXOperandCode::G_V_E_ymm_imm8
+ VEXOperandCode::G_V_E_xmm_imm8
} else {
VEXOperandCode::G_V_E_xmm_imm8
}),
0x0B => (Opcode::VROUNDSD, if L {
- VEXOperandCode::G_V_E_ymm_imm8
+ VEXOperandCode::G_V_E_xmm_imm8
} else {
VEXOperandCode::G_V_E_xmm_imm8
}),
@@ -3269,7 +3269,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
return Err(DecodeError::InvalidOpcode);
} else {
(Opcode::VINSERTF128, if L {
- VEXOperandCode::G_V_E_ymm_imm8
+ VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8
} else {
instruction.opcode = Opcode::Invalid;
return Err(DecodeError::InvalidOpcode);