diff options
| author | iximeow <me@iximeow.net> | 2021-07-04 12:20:13 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-07-04 12:36:03 -0700 |
| commit | 48559b18574b44e2de879a5c641ab602ec22f0d8 (patch) | |
| tree | 0195cd249c1ce2429b12a14d063447fe96e3283e /src/protected_mode/vex.rs | |
| parent | 404cb6e81988ed84a75c89d67bf324409e22a390 (diff) | |
fix several incorrect tests and docs in 64- and 32-bit modes
Diffstat (limited to 'src/protected_mode/vex.rs')
| -rw-r--r-- | src/protected_mode/vex.rs | 28 |
1 files changed, 7 insertions, 21 deletions
diff --git a/src/protected_mode/vex.rs b/src/protected_mode/vex.rs index 053d1aa..3550f77 100644 --- a/src/protected_mode/vex.rs +++ b/src/protected_mode/vex.rs @@ -412,7 +412,7 @@ fn read_vex_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y instruction.opcode = if modrm & 0xc0 == 0xc0 { Opcode::VMOVHLPS } else { - instruction.mem_size = 4; + instruction.mem_size = 8; Opcode::VMOVLPS }; instruction.regs[0] = @@ -1854,7 +1854,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a } else { VEXOperandCode::G_V_E_xmm }), - 0xDA => (Opcode::VPMINSW, if L { + 0xDA => (Opcode::VPMINUB, if L { VEXOperandCode::G_V_E_ymm } else { VEXOperandCode::G_V_E_xmm @@ -3130,12 +3130,12 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a VEXOperandCode::G_E_xmm_imm8 }), 0x0A => (Opcode::VROUNDSS, if L { - VEXOperandCode::G_V_E_ymm_imm8 + VEXOperandCode::G_V_E_xmm_imm8 } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x0B => (Opcode::VROUNDSD, if L { - VEXOperandCode::G_V_E_ymm_imm8 + VEXOperandCode::G_V_E_xmm_imm8 } else { VEXOperandCode::G_V_E_xmm_imm8 }), @@ -3171,14 +3171,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a } else { VEXOperandCode::Ev_G_xmm_imm8 }), - 0x16 => if instruction.prefixes.vex_unchecked().w() { - (Opcode::VPEXTRQ, if L { - instruction.opcode = Opcode::Invalid; - return Err(DecodeError::InvalidOpcode); - } else { - VEXOperandCode::Ev_G_xmm_imm8 - }) - } else { + 0x16 => { (Opcode::VPEXTRD, if L { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOpcode); @@ -3198,7 +3191,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a return Err(DecodeError::InvalidOpcode); } else { (Opcode::VINSERTF128, if L { - VEXOperandCode::G_V_E_ymm_imm8 + VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 } else { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOpcode); @@ -3232,14 +3225,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a } else { VEXOperandCode::G_V_E_xmm_imm8 }), - 0x22 => if instruction.prefixes.vex_unchecked().w() { - (Opcode::VPINSRQ, if L { - instruction.opcode = Opcode::Invalid; - return Err(DecodeError::InvalidOpcode); - } else { - VEXOperandCode::G_V_xmm_Ev_imm8 - }) - } else { + 0x22 => { (Opcode::VPINSRD, if L { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOpcode); |