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authoriximeow <me@iximeow.net>2021-07-02 19:37:56 -0700
committeriximeow <me@iximeow.net>2021-07-02 19:37:56 -0700
commit0b04fd05a955033dc781caaec6eb2b32f85c1b3f (patch)
treeea843ce0d1b8423a33925e6b5f7a478612c1a2d8 /src/protected_mode
parent1d4b7c2dad97694a6980d95287519ba4c3d582ff (diff)
fix several strict rejection for several
Diffstat (limited to 'src/protected_mode')
-rw-r--r--src/protected_mode/mod.rs6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index ac7294f..908e449 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -7562,13 +7562,13 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
}
OperandCode::INV_Gv_M => {
let modrm = read_modrm(words)?;
+ if modrm >= 0xc0 {
+ return Err(DecodeError::InvalidOperand);
+ }
instruction.regs[0] = RegSpec { bank: RegisterBank::D, num: (modrm >> 3) & 7 };
instruction.operands[0] = OperandSpec::RegRRR;
instruction.operands[1] = read_M(words, instruction, modrm)?;
- if instruction.operands[1] == OperandSpec::RegMMM {
- return Err(DecodeError::InvalidOperand);
- }
if [Opcode::LFS, Opcode::LGS, Opcode::LSS].contains(&instruction.opcode) {
if instruction.prefixes.operand_size() {
instruction.mem_size = 4;