diff options
| author | iximeow <me@iximeow.net> | 2026-06-09 07:52:20 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-07-05 00:09:22 +0000 |
| commit | 7bffc21711fcbeeb7b5a38d3297b9b060f54534d (patch) | |
| tree | 3de4421e30da023a1a90a2333a5fcad148332c69 /src/real_mode/vex.rs | |
| parent | 15b8817b2eda4c2f58fc098591677f77c34c454d (diff) | |
fix vgatherdpd using incorrect simd vector width for gather indices
Diffstat (limited to 'src/real_mode/vex.rs')
| -rw-r--r-- | src/real_mode/vex.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/real_mode/vex.rs b/src/real_mode/vex.rs index 3a7fbe3..6a74fe8 100644 --- a/src/real_mode/vex.rs +++ b/src/real_mode/vex.rs @@ -1321,7 +1321,7 @@ fn read_vex_operands< instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; - if instruction.opcode == Opcode::VPGATHERDQ { + if instruction.opcode == Opcode::VPGATHERDQ || instruction.opcode == Opcode::VGATHERDPD { instruction.regs[2].bank = RegisterBank::X; } else { instruction.regs[2].bank = index_bank; |