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authoriximeow <me@iximeow.net>2022-08-27 17:08:29 -0700
committeriximeow <me@iximeow.net>2023-01-02 08:50:23 -0800
commitd2b4f3d1a454c7bbcc487ddfb2839b01dc1c9c9e (patch)
tree003f629e22065e32a07cebd087b3fb1b008b2282 /src/real_mode/vex.rs
parentc75544f724edabc7bd1bf90e4d2ed7ab8ac04507 (diff)
remove a few duplicate impls, add stubs for geneirc translations
generate_opcode.py has quickly grown into generating much more than just opcode definitions, and now handles a few duplicate impls across the different decode modes as well. some of the added impl generation conflicts with still-existing hand-written impls from yore, so they needed a bit of removing. next will be the addition of a generic module for "probably what you want" disassembly of x86, avoiding the 64-/32-/16-bitness of the architecture family with an attempt to decode "probably what you wanted" from a byte sequence. it needs a little more work still, but TODO stubs added here support that new module.
Diffstat (limited to 'src/real_mode/vex.rs')
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