diff options
| author | iximeow <me@iximeow.net> | 2026-05-03 17:48:14 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-05-25 01:33:18 +0000 |
| commit | 351adb926722b626a3fdc85b4d42303d37678fd3 (patch) | |
| tree | 4542a61752e272b559687377c53a77604f149c81 /src | |
| parent | 706ec278edebe06eff9f91f5cb30f5faba46132d (diff) | |
actually support avx/f16c in per-uarch decoding
Diffstat (limited to 'src')
| -rw-r--r-- | src/long_mode/uarch.rs | 2 | ||||
| -rw-r--r-- | src/long_mode/vex.rs | 12 | ||||
| -rw-r--r-- | src/protected_mode/uarch.rs | 2 | ||||
| -rw-r--r-- | src/protected_mode/vex.rs | 12 | ||||
| -rw-r--r-- | src/real_mode/uarch.rs | 2 | ||||
| -rw-r--r-- | src/real_mode/vex.rs | 12 |
6 files changed, 30 insertions, 12 deletions
diff --git a/src/long_mode/uarch.rs b/src/long_mode/uarch.rs index 63fa972..9cfc9de 100644 --- a/src/long_mode/uarch.rs +++ b/src/long_mode/uarch.rs @@ -145,6 +145,7 @@ pub mod amd { .with_rdrand() .with_rdseed() .with_fma3() + .with_f16c() .with_xsavec() .with_xsaves() @@ -272,6 +273,7 @@ pub mod intel { .with_abm() .with_fma3() .with_avx2() + .with_f16c() } /// `Haswell-EX` was a variant of `Haswell` launched in 2015 with functional TSX. these cores diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs index ba39ba1..2f6054a 100644 --- a/src/long_mode/vex.rs +++ b/src/long_mode/vex.rs @@ -2751,11 +2751,15 @@ fn read_vex_instruction< return Err(DecodeError::InvalidOpcode); }) }, - 0x1D => (Opcode::VCVTPS2PH, if L { - VEXOperandCode::E_xmm_G_ymm_imm8 + 0x1D => if instruction.prefixes.vex_unchecked().w() { + return Err(DecodeError::InvalidOpcode); } else { - VEXOperandCode::E_G_xmm_imm8 - }), + (Opcode::VCVTPS2PH, if L { + VEXOperandCode::E_xmm_G_ymm_imm8 + } else { + VEXOperandCode::E_G_xmm_imm8 + }) + }, 0x20 => (Opcode::VPINSRB, if L { return Err(DecodeError::InvalidOpcode); } else { diff --git a/src/protected_mode/uarch.rs b/src/protected_mode/uarch.rs index 6914348..7221747 100644 --- a/src/protected_mode/uarch.rs +++ b/src/protected_mode/uarch.rs @@ -145,6 +145,7 @@ pub mod amd { .with_rdrand() .with_rdseed() .with_fma3() + .with_f16c() .with_xsavec() .with_xsaves() @@ -271,6 +272,7 @@ pub mod intel { .with_abm() .with_fma3() .with_avx2() + .with_f16c() } /// `Haswell-EX` was a variant of `Haswell` launched in 2015 with functional TSX. these cores diff --git a/src/protected_mode/vex.rs b/src/protected_mode/vex.rs index 1b5c9d9..5fa46b9 100644 --- a/src/protected_mode/vex.rs +++ b/src/protected_mode/vex.rs @@ -2616,11 +2616,15 @@ fn read_vex_instruction< return Err(DecodeError::InvalidOpcode); }) }, - 0x1D => (Opcode::VCVTPS2PH, if L { - VEXOperandCode::E_xmm_G_ymm_imm8 + 0x1D => if instruction.prefixes.vex_unchecked().w() { + return Err(DecodeError::InvalidOpcode); } else { - VEXOperandCode::E_G_xmm_imm8 - }), + (Opcode::VCVTPS2PH, if L { + VEXOperandCode::E_xmm_G_ymm_imm8 + } else { + VEXOperandCode::E_G_xmm_imm8 + }) + }, 0x20 => (Opcode::VPINSRB, if L { return Err(DecodeError::InvalidOpcode); } else { diff --git a/src/real_mode/uarch.rs b/src/real_mode/uarch.rs index 8df4213..32dd04a 100644 --- a/src/real_mode/uarch.rs +++ b/src/real_mode/uarch.rs @@ -145,6 +145,7 @@ pub mod amd { .with_rdrand() .with_rdseed() .with_fma3() + .with_f16c() .with_xsavec() .with_xsaves() @@ -271,6 +272,7 @@ pub mod intel { .with_abm() .with_fma3() .with_avx2() + .with_f16c() } /// `Haswell-EX` was a variant of `Haswell` launched in 2015 with functional TSX. these cores diff --git a/src/real_mode/vex.rs b/src/real_mode/vex.rs index 9e24ee8..9651760 100644 --- a/src/real_mode/vex.rs +++ b/src/real_mode/vex.rs @@ -2616,11 +2616,15 @@ fn read_vex_instruction< return Err(DecodeError::InvalidOpcode); }) }, - 0x1D => (Opcode::VCVTPS2PH, if L { - VEXOperandCode::E_xmm_G_ymm_imm8 + 0x1D => if instruction.prefixes.vex_unchecked().w() { + return Err(DecodeError::InvalidOpcode); } else { - VEXOperandCode::E_G_xmm_imm8 - }), + (Opcode::VCVTPS2PH, if L { + VEXOperandCode::E_xmm_G_ymm_imm8 + } else { + VEXOperandCode::E_G_xmm_imm8 + }) + }, 0x20 => (Opcode::VPINSRB, if L { return Err(DecodeError::InvalidOpcode); } else { |