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authoriximeow <me@iximeow.net>2026-06-09 07:52:20 +0000
committeriximeow <me@iximeow.net>2026-07-05 00:09:22 +0000
commit7bffc21711fcbeeb7b5a38d3297b9b060f54534d (patch)
tree3de4421e30da023a1a90a2333a5fcad148332c69 /src
parent15b8817b2eda4c2f58fc098591677f77c34c454d (diff)
fix vgatherdpd using incorrect simd vector width for gather indices
Diffstat (limited to 'src')
-rw-r--r--src/long_mode/vex.rs2
-rw-r--r--src/protected_mode/vex.rs2
-rw-r--r--src/real_mode/vex.rs2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index b787598..3380cf2 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -1408,7 +1408,7 @@ fn read_vex_operands<
instruction.regs[0] =
RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), bank);
let mem_oper = read_E(words, instruction, modrm, bank, sink)?;
- if instruction.opcode == Opcode::VPGATHERDQ {
+ if instruction.opcode == Opcode::VPGATHERDQ || instruction.opcode == Opcode::VGATHERDPD {
instruction.regs[2].bank = RegisterBank::X;
} else {
instruction.regs[2].bank = index_bank;
diff --git a/src/protected_mode/vex.rs b/src/protected_mode/vex.rs
index 429ad23..35ed395 100644
--- a/src/protected_mode/vex.rs
+++ b/src/protected_mode/vex.rs
@@ -1321,7 +1321,7 @@ fn read_vex_operands<
instruction.regs[0] =
RegSpec::from_parts((modrm >> 3) & 7, bank);
let mem_oper = read_E(words, instruction, modrm, bank, sink)?;
- if instruction.opcode == Opcode::VPGATHERDQ {
+ if instruction.opcode == Opcode::VPGATHERDQ || instruction.opcode == Opcode::VGATHERDPD {
instruction.regs[2].bank = RegisterBank::X;
} else {
instruction.regs[2].bank = index_bank;
diff --git a/src/real_mode/vex.rs b/src/real_mode/vex.rs
index 3a7fbe3..6a74fe8 100644
--- a/src/real_mode/vex.rs
+++ b/src/real_mode/vex.rs
@@ -1321,7 +1321,7 @@ fn read_vex_operands<
instruction.regs[0] =
RegSpec::from_parts((modrm >> 3) & 7, bank);
let mem_oper = read_E(words, instruction, modrm, bank, sink)?;
- if instruction.opcode == Opcode::VPGATHERDQ {
+ if instruction.opcode == Opcode::VPGATHERDQ || instruction.opcode == Opcode::VGATHERDPD {
instruction.regs[2].bank = RegisterBank::X;
} else {
instruction.regs[2].bank = index_bank;