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authoriximeow <me@iximeow.net>2026-04-23 07:43:30 +0000
committeriximeow <me@iximeow.net>2026-05-25 00:59:27 +0000
commitabc0978c7d4d331fe047fdcf1acf221754327fd2 (patch)
tree738a24ca85104f676e7fc6ba5b07df827a27c868 /src
parentcabd41fd8c255a464c1436ac502a2317773a83b6 (diff)
cleanup pass on vex-encoded instructions is going to be exciting
Diffstat (limited to 'src')
-rw-r--r--src/long_mode/vex.rs38
-rw-r--r--src/protected_mode/vex.rs38
-rw-r--r--src/real_mode/vex.rs38
3 files changed, 93 insertions, 21 deletions
diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index 2ee9749..b0b900a 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -1755,7 +1755,7 @@ fn read_vex_instruction<
// 0x0a => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8),
// 0x0b => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8),
0x10 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm),
- 0x11 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm),
+ 0x11 => (Opcode::VMOVUPD, VEXOperandCode::E_G_xyLmm),
0x12 => (Opcode::VMOVLPD, if L {
return Err(DecodeError::InvalidOpcode);
} else {
@@ -2073,10 +2073,26 @@ fn read_vex_instruction<
0x09 => (Opcode::VPSIGNW, VEXOperandCode::G_V_E_xyLmm),
0x0A => (Opcode::VPSIGND, VEXOperandCode::G_V_E_xyLmm),
0x0B => (Opcode::VPMULHRSW, VEXOperandCode::G_V_E_xyLmm),
- 0x0C => (Opcode::VPERMILPS, VEXOperandCode::G_V_E_xyLmm),
- 0x0D => (Opcode::VPERMILPD, VEXOperandCode::G_V_E_xyLmm),
- 0x0E => (Opcode::VTESTPS, VEXOperandCode::G_E_xyLmm),
- 0x0F => (Opcode::VTESTPD, VEXOperandCode::G_E_xyLmm),
+ 0x0C => (Opcode::VPERMILPS, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_V_E_xyLmm
+ }),
+ 0x0D => (Opcode::VPERMILPD, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_V_E_xyLmm
+ }),
+ 0x0E => (Opcode::VTESTPS, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm
+ }),
+ 0x0F => (Opcode::VTESTPD, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm
+ }),
0x13 => (Opcode::VCVTPH2PS, VEXOperandCode::G_E_xyLmm),
0x16 => (Opcode::VPERMPS, if L {
if instruction.prefixes.vex_unchecked().w() {
@@ -2614,8 +2630,16 @@ fn read_vex_instruction<
} else {
VEXOperandCode::G_V_E_xyLmm_imm8
}),
- 0x04 => (Opcode::VPERMILPS, VEXOperandCode::G_E_xyLmm_imm8),
- 0x05 => (Opcode::VPERMILPD, VEXOperandCode::G_E_xyLmm_imm8),
+ 0x04 => (Opcode::VPERMILPS, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm_imm8
+ }),
+ 0x05 => (Opcode::VPERMILPD, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm_imm8
+ }),
0x06 => (Opcode::VPERM2F128, if L {
if instruction.prefixes.vex_unchecked().w() {
return Err(DecodeError::InvalidOpcode);
diff --git a/src/protected_mode/vex.rs b/src/protected_mode/vex.rs
index 337e9bc..9144fef 100644
--- a/src/protected_mode/vex.rs
+++ b/src/protected_mode/vex.rs
@@ -1650,7 +1650,7 @@ fn read_vex_instruction<
// 0x0a => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8),
// 0x0b => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8),
0x10 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm),
- 0x11 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm),
+ 0x11 => (Opcode::VMOVUPD, VEXOperandCode::E_G_xyLmm),
0x12 => (Opcode::VMOVLPD, if L {
return Err(DecodeError::InvalidOpcode);
} else {
@@ -1944,10 +1944,26 @@ fn read_vex_instruction<
0x09 => (Opcode::VPSIGNW, VEXOperandCode::G_V_E_xyLmm),
0x0A => (Opcode::VPSIGND, VEXOperandCode::G_V_E_xyLmm),
0x0B => (Opcode::VPMULHRSW, VEXOperandCode::G_V_E_xyLmm),
- 0x0C => (Opcode::VPERMILPS, VEXOperandCode::G_V_E_xyLmm),
- 0x0D => (Opcode::VPERMILPD, VEXOperandCode::G_V_E_xyLmm),
- 0x0E => (Opcode::VTESTPS, VEXOperandCode::G_E_xyLmm),
- 0x0F => (Opcode::VTESTPD, VEXOperandCode::G_E_xyLmm),
+ 0x0C => (Opcode::VPERMILPS, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_V_E_xyLmm
+ }),
+ 0x0D => (Opcode::VPERMILPD, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_V_E_xyLmm
+ }),
+ 0x0E => (Opcode::VTESTPS, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm
+ }),
+ 0x0F => (Opcode::VTESTPD, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm
+ }),
0x13 => (Opcode::VCVTPH2PS, VEXOperandCode::G_E_xyLmm),
0x16 => (Opcode::VPERMPS, if L {
if instruction.prefixes.vex_unchecked().w() {
@@ -2485,8 +2501,16 @@ fn read_vex_instruction<
} else {
VEXOperandCode::G_V_E_xyLmm_imm8
}),
- 0x04 => (Opcode::VPERMILPS, VEXOperandCode::G_E_xyLmm_imm8),
- 0x05 => (Opcode::VPERMILPD, VEXOperandCode::G_E_xyLmm_imm8),
+ 0x04 => (Opcode::VPERMILPS, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm_imm8
+ }),
+ 0x05 => (Opcode::VPERMILPD, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm_imm8
+ }),
0x06 => (Opcode::VPERM2F128, if L {
if instruction.prefixes.vex_unchecked().w() {
return Err(DecodeError::InvalidOpcode);
diff --git a/src/real_mode/vex.rs b/src/real_mode/vex.rs
index afa9565..cf85db9 100644
--- a/src/real_mode/vex.rs
+++ b/src/real_mode/vex.rs
@@ -1650,7 +1650,7 @@ fn read_vex_instruction<
// 0x0a => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8),
// 0x0b => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8),
0x10 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm),
- 0x11 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm),
+ 0x11 => (Opcode::VMOVUPD, VEXOperandCode::E_G_xyLmm),
0x12 => (Opcode::VMOVLPD, if L {
return Err(DecodeError::InvalidOpcode);
} else {
@@ -1944,10 +1944,26 @@ fn read_vex_instruction<
0x09 => (Opcode::VPSIGNW, VEXOperandCode::G_V_E_xyLmm),
0x0A => (Opcode::VPSIGND, VEXOperandCode::G_V_E_xyLmm),
0x0B => (Opcode::VPMULHRSW, VEXOperandCode::G_V_E_xyLmm),
- 0x0C => (Opcode::VPERMILPS, VEXOperandCode::G_V_E_xyLmm),
- 0x0D => (Opcode::VPERMILPD, VEXOperandCode::G_V_E_xyLmm),
- 0x0E => (Opcode::VTESTPS, VEXOperandCode::G_E_xyLmm),
- 0x0F => (Opcode::VTESTPD, VEXOperandCode::G_E_xyLmm),
+ 0x0C => (Opcode::VPERMILPS, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_V_E_xyLmm
+ }),
+ 0x0D => (Opcode::VPERMILPD, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_V_E_xyLmm
+ }),
+ 0x0E => (Opcode::VTESTPS, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm
+ }),
+ 0x0F => (Opcode::VTESTPD, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm
+ }),
0x13 => (Opcode::VCVTPH2PS, VEXOperandCode::G_E_xyLmm),
0x16 => (Opcode::VPERMPS, if L {
if instruction.prefixes.vex_unchecked().w() {
@@ -2485,8 +2501,16 @@ fn read_vex_instruction<
} else {
VEXOperandCode::G_V_E_xyLmm_imm8
}),
- 0x04 => (Opcode::VPERMILPS, VEXOperandCode::G_E_xyLmm_imm8),
- 0x05 => (Opcode::VPERMILPD, VEXOperandCode::G_E_xyLmm_imm8),
+ 0x04 => (Opcode::VPERMILPS, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm_imm8
+ }),
+ 0x05 => (Opcode::VPERMILPD, if instruction.prefixes.vex_unchecked().w() {
+ return Err(DecodeError::InvalidOpcode);
+ } else {
+ VEXOperandCode::G_E_xyLmm_imm8
+ }),
0x06 => (Opcode::VPERM2F128, if L {
if instruction.prefixes.vex_unchecked().w() {
return Err(DecodeError::InvalidOpcode);
generated by cgit v1.1 at 2026-05-25 11:29:45 +0000