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authoriximeow <me@iximeow.net>2023-01-29 17:44:28 -0800
committeriximeow <me@iximeow.net>2023-07-04 19:01:38 -0700
commitbf956fb06a7f9076b2b6879c4b678e41506a0c7c (patch)
tree1953b2b8dfd9e2d890f280160356c15e5a6b8534 /src
parent62102819adcadf8253f27d5ea06953d1400c2dfe (diff)
make operandcode 16b again
Diffstat (limited to 'src')
-rw-r--r--src/long_mode/mod.rs10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 0ba806e..328f18f 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -4862,8 +4862,8 @@ impl OperandCodeBuilder {
OperandCodeBuilder { bits: 0 }
}
- const fn bits(&self) -> u32 {
- self.bits as u32
+ const fn bits(&self) -> u16 {
+ self.bits as u16
}
const fn from_bits(bits: u16) -> Self {
@@ -5026,7 +5026,7 @@ pub struct OperandCodeWrapper { code: OperandCode }
// |
// |
// ---------------------------> read modr/m?
-#[repr(u32)]
+#[repr(u16)]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
enum OperandCode {
Ivs = OperandCodeBuilder::new().special_case(25).bits(),
@@ -6904,7 +6904,7 @@ fn read_operands<
// reversed-operands `movbe` and fairly unlikely. that case is handled in
// `unlikely_operands`. TODO: maybe this could just be a bit in `operand_code` for
// "memory-only mmm"?
- if operand_code.bits() == (OperandCode::Gv_M as u32) {
+ if operand_code.bits() == (OperandCode::Gv_M as u16) {
return Err(DecodeError::InvalidOperand);
}
read_modrm_reg(instruction, words, modrm, bank, sink)?
@@ -6945,7 +6945,7 @@ fn read_operands<
instruction.regs[0].num = ((modrm >> 3) & 7) + if instruction.prefixes.rex_unchecked().r() { 0b1000 } else { 0 };
// for some encodings, the rrr field selects an opcode, not an operand
- if operand_code.bits() != OperandCode::ModRM_0xc1_Ev_Ib as u32 && operand_code.bits() != OperandCode::ModRM_0xff_Ev as u32 {
+ if operand_code.bits() != OperandCode::ModRM_0xc1_Ev_Ib as u16 && operand_code.bits() != OperandCode::ModRM_0xff_Ev as u16 {
sink.record(
modrm_start + 3,
modrm_start + 5,