aboutsummaryrefslogtreecommitdiff
path: root/test/test.rs
diff options
context:
space:
mode:
authoriximeow <me@iximeow.net>2019-12-15 21:19:44 -0800
committeriximeow <me@iximeow.net>2020-01-12 16:10:14 -0800
commit8d8cb8d594217a630dea605348211539afe3f940 (patch)
treea356783767a009d9fe554dd1f88254937ed6cf32 /test/test.rs
parent552ad43802a0152f4a0c3d503bb041cb3c6160d9 (diff)
test fence instructions against different quirks modes
add enclv instruction add sse3, ssse3, sse4.1, and sse4.2 feature flags, plus a host of missing opcodes
Diffstat (limited to 'test/test.rs')
-rw-r--r--test/test.rs11
1 files changed, 7 insertions, 4 deletions
diff --git a/test/test.rs b/test/test.rs
index 5c78c7c..b8c14a7 100644
--- a/test/test.rs
+++ b/test/test.rs
@@ -148,6 +148,7 @@ fn test_0fae() {
let intel = InstDecoder::minimal().with_intel_quirks();
let amd = InstDecoder::minimal().with_amd_quirks();
let default = InstDecoder::default();
+ let minimal = InstDecoder::minimal();
// drawn heavily from "Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group
// Number"
test_display(&[0x0f, 0xae, 0x04, 0x4f], "fxsave [rdi + rcx * 2]");
@@ -163,19 +164,21 @@ fn test_0fae() {
test_display_under(&intel, &[0x0f, 0xae, *modrm], text);
test_display_under(&amd, &[0x0f, 0xae, *modrm], text);
test_display_under(&default, &[0x0f, 0xae, *modrm], text);
- // it turns out intel accepts m != 0 for {l,m,s}fence, but amd does not:
+ test_display_under(&minimal, &[0x0f, 0xae, *modrm], text);
+ // it turns out intel and amd accept m != 0 for {l,m,s}fence:
// from intel:
// ```
// Specification of the instruction's opcode above indicates a ModR/M byte of F0. For this
// instruction, the processor ignores the r/m field of the ModR/M byte. Thus, MFENCE is encoded
// by any opcode of the form 0F AE Fx, where x is in the range 0-7.
// ```
- // whereas amd does not discuss the r/m field at all. it is TBD if amd also ignores the r/m
- // field, but for now assumed to be rejected.
+ // whereas amd does not discuss the r/m field at all. at least as of zen, amd also accepts
+ // these encodings.
for m in 1u8..8u8 {
test_display_under(&intel, &[0x0f, 0xae, modrm | m], text);
- test_invalid_under(&amd, &[0x0f, 0xae, modrm | m]);
+ test_display_under(&amd, &[0x0f, 0xae, modrm | m], text);
test_display_under(&default, &[0x0f, 0xae, modrm | m], text);
+ test_invalid_under(&minimal, &[0x0f, 0xae, modrm | m]);
}
}
}