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2020-05-23fix important memory decode error in long modeiximeow
2020-05-23add SHA, BMI1, and BMI2, complete XSAVE extension supportiximeow
2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
2020-05-03"is there a rep prefix" is something people need to be able to askiximeow
2020-05-03add width() to ask width of an x86 operandiximeow
2020-05-03that instruction is cwd, not cbdiximeow
2020-05-03bump yaxpeax-arch to 0.0.4, use AddressDiff, fix warnings in ffiiximeow
2020-03-23update docs to not be long_mode-specificiximeow
2020-03-22bump to 0.0.10 to fix a warning0.0.10iximeow
2020-03-22yaxpeax-x86 decodes in 32-bit mode nowiximeow
2020-02-22explicitly report x87 as not (yet) supportediximeow
2020-02-22support most avx operand codesiximeow
2020-02-22fix {jmp,call} <reg>, as well as jmpf/callfiximeow
2020-02-22more sse/sse2 supportiximeow
2020-02-22support 660f sse2 instructionsiximeow
2020-02-16embarassingly had OperandSpec variants for modrm displacement == 0 backwardsiximeow
2020-02-11support `in` and `out` instructionsiximeow
2020-02-11add `RegSpec::name` to get `&'static str` labels for registersiximeow
2020-02-11derive Ord and PartialOrd for RegSpec and RegisterBankiximeow
2020-01-15support "int imm8" instructionsiximeow
2020-01-15make space for non-64bit modesiximeow
2020-01-15make x86 actually no_stdiximeow
2020-01-15add more sse2 instructions (packed shift by immediate, mostly)iximeow
2020-01-15add 660f6* series instructions as well as 660f70iximeow
2020-01-15no_std!!iximeow
2020-01-13explicitly fail to handle WAIT prefixiximeow
2020-01-13test that instruction lengths are correctiximeow
2020-01-13add Default impl for Instruction to track yaxpeax-archiximeow
2020-01-13de-pub some internal functionsiximeow
2020-01-12no println when decoding vex instructions pleaseiximeow
2020-01-12"fix warnings"iximeow
2020-01-12match changes in arch to have Resulty decode, instead of Optioniximeow
2020-01-12custom hasher for regspeciximeow
2020-01-12display more directlyiximeow
2020-01-12avx feature flag and avx/aesni instructions flagged properlyiximeow
2020-01-12fix avx bit numberiximeow
2020-01-12support aesniiximeow
2020-01-12support missing sse3 instructions, add tests for sse3 instructionsiximeow
2020-01-12add avx decoder flag, and a display impl showing active featuresiximeow
2020-01-12test fence instructions against different quirks modesiximeow
2020-01-12initial flagging supportiximeow
2020-01-12add a slew of system-y instructions, as well as cpu quirks for amd/intel fenc...iximeow
2020-01-12vex tests work!iximeow
2020-01-12vexiximeow
2020-01-12movs on non-byte operandsiximeow
2020-01-12that wasnt supposed to get committediximeow
2020-01-12proper movs operand supportiximeow
2020-01-12pshuf/psr/shld/shrd plus some test fixesiximeow
2020-01-12down to one failing test, for nowiximeow
2020-01-12more cvt variantsiximeow