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## 0.0.12
* fix improper decode of `sib` memory operand when `rex.x` is set and index is `0b100`
- functionally: instructions which should have had a memory operand like
`[rax + r12 + disp]` were missing `r12`
* add instruction set extensions: `SHA`, `BMI1`, `BMI2`, `XSAVE`, `RDRAND`,
`RDSEED`, `CMPXCHG{8,16}B` `ADX`, `SVM`, `MOVBE`, `PREFETCHW`, `TSX`, and
`F16C`
* add `RDFSBASE`, `RDGSBASE`, `WRFSBASE`, `WRGSBASE`
* builders for per-uarch x86_64 instruction decoders, see `yaxpeax_x86::long_mode::uarch::{intel, amd}`
* builders for per-uarch x86_32 instruction decoders, see `yaxpeax_x86::protected_mode::uarch::{intel, amd}`
## 0.0.11
* fix mis-named 'cbd' instruction, which should be 'cwd'
* add `Operand::width` to query the width of an x86 access
- this is wrong for many memory operands, which require deeper changes
* bump `yaxpeax-arch` to 0.0.4, which yields a breaking change in `Self::Unit` of `LengthedInstruction
* `Prefixes::rep` is now public, allowing users to query if a decoded instruction has a rep prefix
## 0.0.10
same as 0.0.9, but with a warning fixed.
## 0.0.9
added `protected_mode` for 32-bit instruction decoding. BCD instructions not yet supported.
## 0.0.8
same as 0.0.7, but with a readme in the crates.io page.
## 0.0.7
`sse` and `sse2` support are mostly complete.
`jmp reg` erroneously decoded to 32-bit registers without `rex.w`.
`callf` could erroneously decode as having a register operand.
more comprehensive, if yet insufficiently tested, avx decoding.
support `vmclear` and `vmxon`, vmx still incomplete.
## 0.0.6
addressing modes using a sib byte with displacement != 0 were wrongly reported as having no displacement.
## 0.0.5
history basically starts here.
* impl Ord and PartialOrd on RegSpec and RegisterBank
* `RegSpec::name` to get `&'static str` labels for registers
* support `in` and `out` instructions
## 0.0.4 - 0.0.2
seriously stop, just don't use these versions
just bumps to use newer `yaxpeax-arch` since this is all wildly unstable
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