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## 0.1.3
* fix 0x80-opcode instructions not having an opcode
- this meant that for example `lock xorb [rax], 0` would decode as invalid
## 0.1.2
* expose constructors for `RegSpec` in both `long_mode` and `protected_mode`
* expose a const `RegSpec::RIP`
- most useful for matching `Operand::RegDisp(RegSpec::RIP, disp)` in patterns, really
## 0.1.1
* add `long_mode::register_class` and `protected_mode::register_class` where
`RegisterClass` constants for each register class are defined.
- without these, the only way to distinguish register classes would be string compares. bad. sorry!
## 0.1.0
* port `long_mode` improvements to `protected_mode` decoder
- real mode will wait until another day
* support undocumented instruction `salc`
* fix segment registers being numbered wrong
- this is relevant only for mov to/from segments
* support x86_32 `push <segment>``/`pop <segment>`
* support x86_32 `pusha`/`popa`
* support x86_32 BCD instructions
- for `aam`/`aad`, the undocumented `amx` and `adx` forms are used in all cases, including when the base is 10
* begin some proper documentation for public items
/!\ BREAKING CHANGES /!\
* `RegisterBank` is no longer public. `RegisterClass` should be a suitable
replacement, accessible via `reg.class()`, with the register class name
available by `reg.class().name`, and size available by `reg.class().width()`.
`reg.width()` still works, and just forwards to `reg.class().width()`.
* the field `opcode` of `Instruction` is no longer public. it can now be accessed by `inst.opcode()`.
## 0.0.15
* the `x87` instruction set is now fully supported
- textual disassembly differs slightly from other decoders in that
yaxpeax-x86 does not prefer using `st` in place of `st(0)`
* do not decode `into` in 64-bit mode
* support `vmread`, `vmwrite`
* support `iret`/`iretd`/`iretq`
* support `enter`
* support `cmc` and `int1`
* support `loopz`, `loopnz`, `jecxz`
* support `maskmovq`, `movnti`, and `movntq`
- this brings full support to non-vex-coded x86 instructions
* reject excessively-long instructions
* reject reg-reg encodings where instructions forbid those operands
* correctly handle `mov [0xoffset], ax` and `mov ax, [0xoffset]`
- offset had been read with incorrect size
* `vpsrlw`, `vpermq`, `vpminsq`, `vpsrlq`, `vextractf128`, `vinserti128`
* reorganize likely decoding paths for a smidge more speed
## 0.0.14
* `netburst` supported `cmpxchg16b` from its first x86_64 incarnation. since no
uarch in `long_mode` had declared `cmpxchg16b` support, no uarch-specific Intel
decoder supported `cmpxchg16b`.
## 0.0.13
* the Intel microarchitecture is named `Penryn`, not `Peryn`.
## 0.0.12
* fix improper decode of `sib` memory operand when `rex.x` is set and index is `0b100`
- functionally: instructions which should have had a memory operand like
`[rax + r12 + disp]` were missing `r12`
* add instruction set extensions: `SHA`, `BMI1`, `BMI2`, `XSAVE`, `RDRAND`,
`RDSEED`, `CMPXCHG{8,16}B` `ADX`, `SVM`, `MOVBE`, `PREFETCHW`, `TSX`, and
`F16C`
* add `RDFSBASE`, `RDGSBASE`, `WRFSBASE`, `WRGSBASE`
* builders for per-uarch x86_64 instruction decoders, see `yaxpeax_x86::long_mode::uarch::{intel, amd}`
* builders for per-uarch x86_32 instruction decoders, see `yaxpeax_x86::protected_mode::uarch::{intel, amd}`
## 0.0.11
* fix mis-named 'cbd' instruction, which should be 'cwd'
* add `Operand::width` to query the width of an x86 access
- this is wrong for many memory operands, which require deeper changes
* bump `yaxpeax-arch` to 0.0.4, which yields a breaking change in `Self::Unit` of `LengthedInstruction
* `Prefixes::rep` is now public, allowing users to query if a decoded instruction has a rep prefix
## 0.0.10
same as 0.0.9, but with a warning fixed.
## 0.0.9
added `protected_mode` for 32-bit instruction decoding. BCD instructions not yet supported.
## 0.0.8
same as 0.0.7, but with a readme in the crates.io page.
## 0.0.7
`sse` and `sse2` support are mostly complete.
`jmp reg` erroneously decoded to 32-bit registers without `rex.w`.
`callf` could erroneously decode as having a register operand.
more comprehensive, if yet insufficiently tested, avx decoding.
support `vmclear` and `vmxon`, vmx still incomplete.
## 0.0.6
addressing modes using a sib byte with displacement != 0 were wrongly reported as having no displacement.
## 0.0.5
history basically starts here.
* impl Ord and PartialOrd on RegSpec and RegisterBank
* `RegSpec::name` to get `&'static str` labels for registers
* support `in` and `out` instructions
## 0.0.4 - 0.0.2
seriously stop, just don't use these versions
just bumps to use newer `yaxpeax-arch` since this is all wildly unstable
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