diff options
| author | iximeow <me@iximeow.net> | 2026-09-11 17:05:03 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-09-11 17:05:03 +0000 |
| commit | 3d645f4fd918af427e4b3ade56057966f4ac894f (patch) | |
| tree | 6d53d1dee50a6608ae068572865ce7267038ff5a | |
| parent | 0eb1d9d89c78c6a5b0f49951b233a8ad63b62f5b (diff) | |
fix some lingering warnings
| -rw-r--r-- | src/armv7/display.rs | 2 | ||||
| -rw-r--r-- | src/armv7/thumb.rs | 10 | ||||
| -rw-r--r-- | tests/armv7/mod.rs | 1 |
3 files changed, 9 insertions, 4 deletions
diff --git a/src/armv7/display.rs b/src/armv7/display.rs index d8d67a2..ba89f50 100644 --- a/src/armv7/display.rs +++ b/src/armv7/display.rs @@ -1554,7 +1554,7 @@ mod buffer_sink { /// into. /// /// SAFETY: callers must print at most one instruction into this handle. - unsafe fn write_handle(&mut self) -> yaxpeax_arch::display::InstructionTextSink { + unsafe fn write_handle(&mut self) -> yaxpeax_arch::display::InstructionTextSink<'_> { self.content.clear(); // Safety: `content` was just cleared, so writing begins at the start of the buffer. // `content`is large enough to hold a fully-formatted instruction (see diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs index b59754c..e8b050a 100644 --- a/src/armv7/thumb.rs +++ b/src/armv7/thumb.rs @@ -1,3 +1,7 @@ +// names from the manual are like, `Rt`, `CRd`, etc, which are not typical snake +// case and provoke style warnings. +#![allow(non_snake_case)] + use yaxpeax_arch::Arch; use crate::armv7::{ @@ -4467,7 +4471,7 @@ fn decode_table_a6_30(decoder: &InstDecoder, inst: &mut Instruction, instr2: Bit // MCR, MCR2 (A8-477) inst.opcode = Opcode::MCR(coproc, opc1, opc2, is_2); inst.operands = [ - Operand::Reg(Reg::from_u8(CRd)), + Operand::Reg(Reg::from_u8(Rt)), Operand::CReg(CReg::from_u8(CRn)), Operand::CReg(CReg::from_u8(CRm)), Operand::Nothing, @@ -4475,10 +4479,10 @@ fn decode_table_a6_30(decoder: &InstDecoder, inst: &mut Instruction, instr2: Bit } else { // MRC, MRC2 (A8-493) inst.opcode = Opcode::MRC(coproc, opc1, opc2, is_2); - let dest = if CRd == 0b1111 { + let dest = if Rt == 0b1111 { Operand::StatusRegMask(StatusRegMask::APSR_NZCV) } else { - Operand::Reg(Reg::from_u8(CRd)) + Operand::Reg(Reg::from_u8(Rt)) }; inst.operands = [ dest, diff --git a/tests/armv7/mod.rs b/tests/armv7/mod.rs index b5d5d17..55f756f 100644 --- a/tests/armv7/mod.rs +++ b/tests/armv7/mod.rs @@ -729,6 +729,7 @@ fn test_decode_mul() { ); } +#[test] fn test_register_shift_rotate() { test_armv6([0xec, 0x02, 0x00, 0x00], "andeq r0, r0, ip, ror 5"); test_armv6([0xa0, 0x33, 0x0b, 0x00], "andeq r3, fp, r0, lsr 7"); |