fix ssat/16 second operand off by one, testcases

1 files changed, 3 insertions, 0 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 19dd69b..60dd00d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -32,6 +32,9 @@
   behavior as "unpredictable", but capstone and others report this as a
   post-index as the bits imply. yaxpeax will still reject this encoding if
   configured to reject unpredictable instructions.
+* thumb2: fix ssat and ssat16's second operand being decoded off-by-one.
+  the field is 1-based rather than 0-based, so for example an instruction which
+  had that operand as "1" was incorrectly decoded as being "0"
 * ARMv7: do not try to elide memory offset when 0 in postindex operands.
   this makes a post-index (and implied writeback!) ambiguous with a pre-indexed
   access with offset zero. that is, `[r1, 0]` may be written as `[r1]`, but