| Age | Commit message (Expand) | Author |
|---|
| 2 hours | report rounding bit of smmla/smmls | iximeow |
| 3 hours | fix hvc immediate missing its upper four bits | iximeow |
| 3 hours | fix ssat/16 second operand off by one, testcases | iximeow |
| 3 hours | fix issues around unpredictable ldrd and offset printing | iximeow |
| 3 hours | fix {s,u}xt{h,b}[16] using an immediate to describe their rotates | iximeow |
| 3 hours | fix mrc/mrc2 use of CRd=15 | iximeow |
| 2026-08-04 | write condition code *before* .w suffix | iximeow |
| 2026-08-04 | msr confusion like with mrs.. | iximeow |
| 2026-08-03 | armv8 thumb-mode hints | iximeow |
| 2026-08-03 | decode unknown wide hints like any other hints | iximeow |
| 2026-08-02 | fix swapped rfe{ia,db} and srs{ia,db} | iximeow |
| 2026-08-02 | fix missing decode of `s` bit for wide shift/rotate ops | iximeow |
| 2026-08-02 | thumb ldc/stc encodings missed a bit | iximeow |
| 2026-08-02 | sufficiently advanced SIMD is indistinguishable from coprocessors | iximeow |
| 2026-08-02 | thumb2 preload improvements | iximeow |
| 2026-08-02 | thumb SIMD encoding should have returned Incomplete | iximeow |
| 2026-08-02 | pkhbt/pkhtb bitmask confusion | iximeow |
| 2026-08-02 | Test Target, fix bogus MRS destinations | iximeow |
| 2026-08-02 | ldrexd changelog | iximeow |
| 2026-07-28 | thumb2: fix parallel addition/subtraction, (un)signed | iximeow |
| 2026-07-28 | fix thumb2 TBH decode: wrong opcode and register-shift operand | Brandon Ros |
| 2026-07-28 | fix more thumb2 register data-processing decode bugs | Brandon Ros |
| 2026-07-28 | fix several thumb2 decode bugs | Brandon Ros |
| 2026-07-28 | Decode the correct number of operands for TST/TEQ (immediate/register) | Grond |
| 2026-07-28 | Decode the correct number of operands for CMP/CMN (immediate/register) | Grond |
| 2026-07-28 | Fix the handling of reserved bits in uncommon loads/stores | Grond |
| 2026-07-28 | Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2 | Grond |
| 2026-07-28 | Implement the RRX immediate shift type | Grond |
| 2026-07-28 | Fix the handling of arithmetic register shifts with zero immediates | Grond |
| 2026-06-19 | Add armv7::InstDecoder::in_thumb_mode() method | Samuel Arnold |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 |
| 2026-02-22 | derive Clone and Copy for armv7 instruction | rva3 |
| 2025-10-19 | update changelog, no 0.3.2 after all | iximeow |
| 2025-10-19 | tag instruction decode fixes, differential test precision | iximeow |
| 2025-06-20 | changelog + another inline | iximeow |
| 2025-02-06 | 0.3.10.3.1 | iximeow |
| 2024-06-25 | 0.3.00.3.0 | iximeow |
| 2024-06-25 | include udf note in changelog | iximeow |
| 2024-03-09 | 0.2.50.2.5 | iximeow |
| 2023-11-02 | another changelog update, this time actually followed by a release... | iximeow |
| 2023-04-25 | prepare changelog updates | iximeow |
| 2022-01-02 | 0.2.3 | iximeow |
| 2022-01-02 | fix docs typo0.2.2 | iximeow |
| 2022-01-02 | 0.2.10.2.1 | iximeow |
| 2022-01-02 | document the crate | iximeow |
| 2022-01-01 | 0.1.4 | iximeow |
| 2021-09-28 | do not publish crates with compilation warnings (bump for 0.1.3 also)0.1.3 | iximeow |
| 2021-09-28 | handle another unintended panic in display impl | iximeow |
| 2021-09-28 | fix various armv8 and armv8 panics that should be Err. | iximeow |
| 2021-07-21 | fix DecodeError impl on builds using yaxpeax-arch+std0.1.1 | iximeow |
