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| author | iximeow <me@iximeow.net> | 2026-09-11 16:15:14 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-09-11 16:19:27 +0000 |
| commit | 475321a686f346ac51cded60384a903fa8e9fdf8 (patch) | |
| tree | 4aa7514bfc80d4042db303a6fc0943e7adcc1714 /CHANGELOG | |
| parent | cf151c1dc6926bf7d14eb5a50afe42b79e6fd481 (diff) | |
fix hvc immediate missing its upper four bits
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -35,6 +35,7 @@ * thumb2: fix ssat and ssat16's second operand being decoded off-by-one. the field is 1-based rather than 0-based, so for example an instruction which had that operand as "1" was incorrectly decoded as being "0" +* thumb2: fix `hvc` immediate missing its upper four bits * ARMv7: do not try to elide memory offset when 0 in postindex operands. this makes a post-index (and implied writeback!) ambiguous with a pre-indexed access with offset zero. that is, `[r1, 0]` may be written as `[r1]`, but |
