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| author | iximeow <me@iximeow.net> | 2026-08-03 00:25:39 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-08-03 00:25:39 +0000 |
| commit | ee19aba4c34f495d29c87b6d2c9d32614ba62cf8 (patch) | |
| tree | 0a8b685c4dfe3328cf3a58e5c83ca32b9a69b8c9 /CHANGELOG | |
| parent | 1158b671a39d01ce3de822c814d4d3bae3466918 (diff) | |
decode unknown wide hints like any other hints
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -17,6 +17,8 @@ * thumb2: some coprocessor instructions were incorrectly decoded as `ldc*/stc*` * thumb2: fix missing decode of `s` bit for wide lsl/lsr/asr/ror (register) * thumb2: rfeia and rfedb were decoded backwards. likewise for srsia and srsdb +* thumb2: unknown wide hints are decoded as `hint` like other cases in ARM, + rather than rejected as invalid * ARMv8: support thumb2 encoding of `Test Target` instruction, `Opcode::TT` (formatted as any of `tt`, `ttt`, `tta`, `ttat`) * ARMv8: formerly-coprocessor instructions have been defined into SIMD extensions, |
